PSD4235G2-90UI STMicroelectronics, PSD4235G2-90UI Datasheet - Page 85

• Manufacturer Part Number: PSD4235G2-90UI
• Description: IC FLASH 4MBIT 90NS 80TQFP
• Manufacturer: STMicroelectronics

Specifications of PSD4235G2-90UI

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 4M (512K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1969

PSD4235G2
20.9
20.10
Figure 27. Peripheral I/O mode
JTAG in-system programming (ISP)
Port E is JTAG compliant, and can be used for In-System Programming (ISP). You can
multiplex JTAG operations with other functions on Port E because In-System Programming
(ISP) is not performed during normal system operation. For more information on the JTAG
Port, see
MCU Reset mode
Ports F and G can be configured to operate in MCU Reset mode. This mode is available
when PSD is configured for the Motorola 16-bit 683xx and HC16 family and is active only
during reset.
At the rising edge of the Reset input, the MCU reads the logic level on the data bus (D15-
D0) pins. The MCU then configures some of its I/O pin functions according to the logic level
input on the data bus lines. Two dedicated buffers are usually enabled during reset to drive
the data bus lines to the desired logic level.
The PSD can replace the two buffers by configuring Ports F and G to operate in MCU Reset
mode. In this mode, the PSD will drive the pre-defined logic level or data pattern on to the
MCU data bus when Reset is active and there is no ongoing bus cycle. After reset, Ports F
and G return to the normal Data Port mode.
The MCU Reset mode is enabled and configured in PSDsoft Express. The user defines the
logic level (data pattern) that will be drive out from Ports F and G during reset.
Figure 33: Reset (RESET)
RD
PSEL0
PSEL1
VM REGISTER BIT 7
WR
PSEL
timing.
DATA BUS
D0 - D7
PA0 - PA7
I/O ports
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