IDT70824L25PF IDT, Integrated Device Technology Inc, IDT70824L25PF Datasheet - Page 18

• Manufacturer Part Number: IDT70824L25PF
• Description: IC SARAM 64KBIT 25NS 80TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70824L25PF

• Format - Memory: RAM
• Memory Type: SARAM
• Memory Size: 64K (4K x 16)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70824L25PF

Waveform of Write Cycles: Sequential Port (STRT/EOB Flag Timing)
NOTES: (Also used in Figure "Read STRT/EOB Flag Timing")
1. If SSTRT
2. If CNTEN = V
3. SOE will control the output and should be HIGH on power-up. If SCE = V
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = V
6. SOE = V
SSTRT
SI/O
IDT70824S/L
High-Speed 4K x 16 Sequential Access Random Access Memory
CNTEN
EOB
cycle. If SCE = V
contention and permit a write on this cycle.
SI/O
SCLK
SR/W
SOE
SCE
OUT
1/2
1/2
IN
IL
1
or SSTRT
makes no difference at this point since the SR/W = V
IL
, data would be written to D
IH
t
t
for the SCLK's rising edge, the internal address counter will not advance.
WS
WS
IL
Dx
and is clocked in while SR/W = V
2
= V
t
t
WH
WH
t
IL
CH
, then address will be clocked in on the SCLK's rising edge.
HIGH IMPEDANCE
t
ES
t
CL
(3)
D0
0
again since CNTEN = V
t
IL
EH
, the data addressed will be written to if the last cycle was a read. SOE may be used to control the bus
(1)
t
t
t
DS
WS
WS
D1
IL
disables the output until SR/W = V
IH
.
t
t
(4)
WH
WH
IL
and is clocked in while SR/W = V
t
18
DH
t
ES
D2
t
EH
IH
Military and Commercial Temperature Ranges
is clocked in on the next rising clock edge.
t
EB
IH
D3
, the data addressed will be read out within that
(6)
HIGH IMPEDANCE
(5)
(2)
t
t
CD
CKLZ
3099 drw 22
D3