MT46H8M16LFCF-10 IT Micron Technology Inc, MT46H8M16LFCF-10 IT Datasheet - Page 45

• Manufacturer Part Number: MT46H8M16LFCF-10 IT
• Description: IC DDR SDRAM 128MBIT 60VFBGA
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H8M16LFCF-10 IT

• Format - Memory: RAM
• Memory Type: Mobile DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 60-VFBGA
• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 15b
• Access Time (max): 7ns
• Maximum Clock Rate: 104MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11:
PDF: 09005aef822b7e27/Source: 09005aef822b7dd6
MT46H8M16LFB_2.fm - Rev. A 5/06 EN
(auto precharge
(auto precharge
Current State
precharging
precharge)
precharge)
activating,
(with auto
(with auto
active, or
disabled)
disabled)
Write
Write
Read
Read
Row
Any
Idle
Truth Table – Current State Bank n - Command to Bank m
Notes: 1–6; notes appear below and on next page
Notes:
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
2. This table describes alternate bank operation, except where noted (i.e., the current state is
3. Current state definitions:
1. This table applies when CKE
3a. The read with auto precharge enabled or WRITE with auto precharge enabled
RAS#
the previous state was self refresh) or after
power-down).
for bank n and the commands shown are those allowed to be issued to bank m, assuming
that bank m is in such a state that given command is allowable). Exceptions are covered in
the notes below.
Read with auto precharge enabled: See following text – 3a
Write with auto precharge enabled: See following text – 3a
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
states can each be broken into two parts: the access period and the precharge
period. For read with auto precharge, the precharge period is defined as if the
same burst was executed with auto precharge disabled and then followed with
the earliest possible PRECHARGE command that still accesses all of the data in
the burst. For write with auto precharge, the precharge period begins when
Row active: A row in the bank has been activated, and
CAS#
X
H
X
H
H
H
H
H
H
H
H
H
H
Write: A WRITE burst has been initiated, with auto precharge disabled, and has
L
L
L
L
L
L
L
L
L
L
Read: A READ burst has been initiated, with auto precharge disabled, and has not
Idle: The bank has been precharged, and
bursts/accesses and no register accesses are in progress.
yet terminated or been terminated.
not yet terminated or been terminated.
WE#
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
n-1
45
was HIGH and CKE
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Command/Action
t
PDX has been met (if the previous state was
n
is HIGH and after
t
RP has been met.
t
RCD has been met. No data
©2006 Micron Technology, Inc. All rights reserved.
t
XSR has been met (if
Truth Tables
7, 9, 3a
Notes
Advance
7, 3a
7, 3a
7, 3a
7, 9
7, 8
7
7
7
7