MT47H64M8CB-5E:B Micron Technology Inc, MT47H64M8CB-5E:B Datasheet - Page 25

• Manufacturer Part Number: MT47H64M8CB-5E:B
• Description: IC DDR2 SDRAM 512MBIT 5NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-5E:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Output Drive Strength
DQS# Enable/Disable
RDQS Enable/Disable
Output Enable/Disable
On-Die Termination (ODT)
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
The output drive strength is defined by bit E1, as shown in Figure 10 on page 24. The
normal drive strength for all outputs are specified to be SSTL_18. Programming bit E1 = 0
selects normal (full strength) drive strength for all outputs. Selecting a reduced drive
strength option (E1 = 1) will reduce all outputs to approximately 60 percent of the
SSTL_18 drive strength. This option is intended for the support of lighter load and/or
point-to-point environments.
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the
differential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a
single-ended mode and the DQS# ball is disabled. When disabled, DQS# should be left
floating. This function is also used to enable/disable RDQS#. If RDQS is enabled (E11 =
1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled.
The RDQS ball is enabled by bit E11, as shown in Figure 10 on page 24. This feature is
only applicable to the x8 configuration. When enabled (E11 = 1), RDQS is identical in
function and timing to data strobe DQS during a READ. During a WRITE operation,
RDQS is ignored by the DDR2 SDRAM.
The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 10 on page 24.
When enabled (E12 = 0), all outputs (DQs, DQS, DQS#, RDQS, RDQS#) function
normally. When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS,
RDQS#) are disabled, thus removing output buffer current. The output disable feature is
intended to be used during I
ODT effective resistance, R
Figure 10 on page 24. The ODT feature is designed to improve signal integrity of the
memory channel by allowing the DDR2 SDRAM controller to independently turn on/off
ODT for any or all devices. R
selectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/
LDQS#, DM, and UDM/LDM signals. Bits (E6, E2) determine what ODT resistance is
enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is
selected by enabling switch “sw1,” which enables all R1 values that are 150Ω each,
enabling an effective resistance of 75Ω (R
all R2 values that are 300Ω each, enable an effective ODT resistance of 150Ω (R
= R2/2). Switch “sw3” enables R1 values of 100Ω, enabling effective resistance of 50Ω.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
The ODT control ball is used to determine when R
assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and
ODT input ball are only used during active, active power-down (both fast-exit and slow-
exit modes), and precharge power-down modes of operation. ODT must be turned off
prior to entering self refresh. During power-up and initialization of the DDR2 SDRAM,
ODT should be disabled until issuing the EMR command to enable the ODT feature, at
TT
DD
TT
(EFF), is defined by bits E2 and E6 of the EMR, as shown in
25
effective resistance values of 50Ω, 75Ω, and 150Ω are
characterization of read current.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TT
2
(
512Mb: x4, x8, x16 DDR2 SDRAM
EFF
)
TT
= R2/2). Similarly, if “sw2” is enabled,
(EFF) is turned on and off,
Output Drive Strength
©2004 Micron Technology, Inc. All rights reserved.
TT
2
(
EFF
)