MT48V8M16LFB4-10:G Micron Technology Inc, MT48V8M16LFB4-10:G Datasheet - Page 43
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MT48V8M16LFB4-10:G
Manufacturer Part Number
MT48V8M16LFB4-10:G
Description
IC SDRAM 128MBIT 100MHZ 54VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT48LC8M16LFB4-75MG_TR.pdf
(80 pages)
Specifications of MT48V8M16LFB4-10:G
Format - Memory
RAM
Memory Type
Mobile SDRAM
Memory Size
128M (8Mx16)
Speed
100MHz
Interface
Parallel
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-VFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48V8M16LFB4-10:G
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT48V8M16LFB4-10:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Figure 33:
Figure 34:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
WRITE With Auto Precharge Interrupted by a READ
WRITE With Auto Precharge Interrupted by a WRITE
Internal
States
Internal
States
Notes:
Notes:
COMMAND
COMMAND
ADDRESS
ADDRESS
BANK m
BANK m
BANK n
BANK n
• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
1. DQM is LOW.
1. DQM is LOW.
CLK
CLK
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after
valid data WRITE to bank n will be data registered 1 clock prior to a WRITE to bank m
(Figure 34).
DQ
DQ
t
WR is met, where
Page Active
Page Active
T0
NOP
T0
NOP
WRITE - AP
WRITE - AP
BANK n,
BANK n,
Page Active
Page Active
BANK n
BANK n
COL a
COL a
T1
D
T1
D
a
a
IN
IN
WRITE with Burst of 4
WRITE with Burst of 4
a + 1
a + 1
T2
T2
D
D
NOP
NOP
IN
IN
t
WR begins when the WRITE to bank m is registered. The last
43
BANK m,
READ - AP
a + 2
T3
COL d
T3
BANK m
D
NOP
IN
Interrupt Burst, Write-Back
t
WR - BANK n
READ with Burst of 4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK m,
TRANSITIONING DATA
WRITE - AP
TRANSITIONING DATA
COL d
BANK m
T4
T4
D
NOP
CL = 3 (BANK m)
t
d
IN
WR - BANK n
Interrupt Burst, Write-Back
WRITE with Burst of 4
128Mb: x16, x32 Mobile SDRAM
T5
T5
d + 1
NOP
NOP
D
IN
Precharge
t
RP - BANK n
T6
T6
d + 2
D
NOP
D
NOP
OUT
t RP - BANK n
d
IN
Precharge
DON’T CARE
DON’T CARE
©2001 Micron Technology, Inc. All rights reserved.
T7
T7
d + 3
D
d + 1
NOP
NOP
D
t WR - BANK m
t RP - BANK m
OUT
IN
Write-Back
READs