MT45V256KW16PEGA-55 WT TR Micron Technology Inc, MT45V256KW16PEGA-55 WT TR Datasheet
MT45V256KW16PEGA-55 WT TR
Specifications of MT45V256KW16PEGA-55 WT TR
Related parts for MT45V256KW16PEGA-55 WT TR
MT45V256KW16PEGA-55 WT TR Summary of contents
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... DQ2 D VssQ DQ11 A17 A7 DQ3 Vcc E VccQ DQ12 NC Vss A16 DQ4 F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 NC A12 A13 WE# DQ7 H DNU A8 A9 A10 A11 NC Top view (Ball down) Part Number Example: MT45V256KW16PEGA-55WT ©2007 Micron Technology, Inc. All rights reserved. Features ...
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... Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Timing Diagrams .21 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Revision History .26 PDF: 09005aef832450a3/Source: 09005aef82f264aa 4mb_ap_3v_psram_p22zTOC.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 Table of Contents ©2007 Micron Technology, Inc. All rights reserved. ...
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... Figure 22: WRITE Cycle (CE# Control .23 Figure 23: WRITE Cycle (LB#/UB# Control .24 Figure 24: 48-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 PDF: 09005aef832450a3/Source: 09005aef82f264aa 4mb_ap_3v_psram_p22zLOF.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K . .22 IH Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 List of Figures ©2007 Micron Technology, Inc. All rights reserved. ...
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... Deep Power-Down Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 11: Initialization Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 PDF: 09005aef832450a3/Source: 09005aef82f264aa 4mb_ap_3v_psram_p22zLOT.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 List of Tables ©2007 Micron Technology, Inc. All rights reserved. ...
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... For seamless operation on an asynchronous memory bus, PSRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write performance. A user-accessible configuration register (CR) defines how the PSRAM device performs on-chip refresh and whether page mode read accesses are permitted ...
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... PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Description Address inputs: Inputs for the address accessed during READ or WRITE operations. The address lines are also used to define the value to be loaded into the CR. ...
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... The device will consume active power in this mode whenever addresses are changed current. 6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Power CE# WE# Standby H X ...
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... CSN-11, “Product Mark/Label,” at www.micron.com/csn. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K 256K -55 to verify that the part number is offered and valid. If the Micron Technology, Inc ...
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... PSRAM products that are popular in low-power, portable applications. MT45V256KW16PE devices contain an 4,194,304-bit DRAM core organized as 262,144 addresses by 16 bits. These devices include the industry-standard, asynchronous memory interface found on other low-power SRAM or PSRAM offerings. Page mode access is also supported as a bandwidth-enhancing extension to the asyn- chronous read protocol. ...
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... LB#/UB# Figure 6: WRITE Operation CE# OE# WE# Address Data LB#/UB# PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Valid address Valid data READ cycle time Don’t Care t < CEM Valid address Valid data WRITE cycle time Don’ ...
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... During READ operations, enabled bytes are driven onto the DQ. The DQ signals associated with a disabled byte are put into a High-Z state during a READ opera- tion. During WRITE operations, disabled bytes are not transferred to the memory array, and the internal value remains unchanged. During a WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first ...
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... Partial-array refresh (PAR) restricts REFRESH operation to a portion of the total memory array. This feature enables the system to reduce refresh current by only refreshing that part of the memory array that is absolutely necessary. The refresh options are “full array” and “none of the array.” Data stored in addresses not receiving refresh will become corrupted ...
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... Driving ZZ# LOW puts the device in PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). The device should not be put into DPD using the CR software-access sequence. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Power-up To enable PAR, bring ZZ# LOW for 10µs ...
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... CR on the rising edge of CE# or WE#, whichever occurs first. LB#/UB# are “Don’t Care.” Access using ZZ# is WRITE only. Figure 10: Load Configuration Register Operation Using ZZ# Address CE# WE# ZZ# PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K ...
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... OE# WE# LB#/UB# Data Notes possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K the system will use DPD; DPD cannot be enabled or disabled using ...
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... LB#/UB# Data Notes possible that the data stored at the highest memory location will be altered if the data at the falling edge of WE# is not 0000h. Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh The PAR bits restrict REFRESH operation to a portion of the total memory array. The refresh options are “ ...
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... I SB inputs must be driven to V power-up or when entering standby mode. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K relative to V –0. ≤ +85 ºC); Industrial temperature (–40ºC < ...
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... Deep power-down Table 6: Capacitance Specifications and Conditions Description Input capacitance Input/output capacitance (DQ) Notes: 1. These parameters are verified in device characterization and are not 100% tested. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K Temperature (°C) Conditions 0V; +25° ...
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... High-Z to Low-Z timings are tested with the circuit shown in Figure 15 on page 19. The Low- Z timings measure a 100mV transition away from the High Page mode enabled only. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K Q/2 Test points CC Q for a logic 1 and V CC Q/2 ...
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... Write pulse width Write recovery time ZZ# LOW to WE# LOW Table 10: Deep Power-Down Timing Requirements Description Chip deselect to ZZ# LOW Deep power-down recovery Minimum ZZ# pulse width PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 -55 Symbol Min Max – – ...
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... Power-Up Initialization Period Vcc, VccQ = 2.7V Figure 17: Load Configuration Register Address CE# LB#/UB# WE# OE# ZZ# Figure 18: Deep Power-Down Entry and Exit ZZ# CE# PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Symbol OPCODE CDZZ t ZZWE t CDZZ t ZZ (MIN) 21 ...
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... Address CE# LB#/UB# OE# Data out Figure 20: Page Mode READ Operation (WE Address A[17:4] Address A[3:0] CE# LB#/UB# OE# Data out PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K Valid address BHZ BLZ t OHZ OLZ High-Z Valid data Don’t Care ...
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... Address CE# LB#/UB# WE# OE# Data in Data out Figure 22: WRITE Cycle (CE# Control) Address CE# LB#/UB# WE# OE# Data in Data out PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K Valid address WPH Valid data t WHZ t OW High-Z Don’t Care t WC ...
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... Figure 23: WRITE Cycle (LB#/UB# Control) Address CE# LB#/UB# WE# OE# Data in Data out PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K Valid address Valid data WHZ High-Z Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Although considered final, these specifications are subject to change, as further product development and data characterization some- PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 3.75 0.75 TYP ...
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... Changed to production status. Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/08 • Initial release. PDF: 09005aef832450a3/Source: 09005aef82f264aa 8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN 4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. 26 Revision History ©2007 Micron Technology, Inc. All rights reserved. ...