MT45V256KW16PEGA-55 WT TR Micron Technology Inc, MT45V256KW16PEGA-55 WT TR Datasheet - Page 16

• Manufacturer Part Number: MT45V256KW16PEGA-55 WT TR
• Description: IC PSRAM 4MBIT 55NS 48VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45V256KW16PEGA-55 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 4M (256K x 16)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 48-VFBGA
• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1415-2

Figure 12:
Partial-Array Refresh (CR[2:0]) Default = Full-Array Refresh
Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled
Page Mode READ Operation (CR[7]) Default = Disabled
PDF: 09005aef832450a3/Source: 09005aef82f264aa
8mb_4mb_ap_3v_psram_p22z__2.fm - Rev. B 4/08 EN
Read Configuration Register
Notes:
LB#/UB#
1. It is possible that the data stored at the highest memory location will be altered if the data
The PAR bits restrict REFRESH operation to a portion of the total memory array. The
refresh options are “full array” and “none of the array.”
The sleep mode bit defines the low-power mode to be entered when ZZ# is driven LOW.
If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is enabled. PAR can
also be enabled directly by writing to the CR using the software-access sequence. Note
that this disables ZZ# initiation of PAR. DPD cannot properly be enabled or disabled
using the software-access sequence; DPD should only be enabled or disabled using ZZ#
to access the CR.
DPD operation disables all refresh-related activity. This mode is used when the system
does not require the storage provided by the PSRAM device. When DPD is enabled, any
stored data will become corrupted. When refresh activity has been re-enabled, the
PSRAM device will require 150µs to perform an initialization procedure before normal
operation can resume. DPD should not be enabled using CR software access.
The page mode operation bit determines whether page mode READ operations are
enabled. In the power-up default state, page mode is disabled.
Address
at the falling edge of WE# is not 0000h.
Data
WE#
OE#
CE#
Address
XXXXh
(MAX)
READ
4Mb: 3.0V Core Async/Page PSRAM Memory 256K x 16
Address
XXXXh
(MAX)
READ
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
CR: 0000h
Address
WRITE
(MAX)
0ns (MIN), see Note 1
Configuration Register Operation
Address
READ
(MAX)
Don’t Care
CR value
out
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