M58LW032D110N6 STMicroelectronics, M58LW032D110N6 Datasheet

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M58LW032D110N6

Manufacturer Part Number
M58LW032D110N6
Description
IC FLASH 32MBIT 110NS 56TSOP
Manufacturer
STMicroelectronics
Datasheet

Specifications of M58LW032D110N6

Format - Memory
FLASH
Memory Type
FLASH - Nor
Memory Size
32M (4Mx8, 2Mx16)
Speed
110ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
56-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-1725

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FEATURES SUMMARY
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August 2004
WIDE x8 or x16 DATA BUS for HIGH
BANDWIDTH
SUPPLY VOLTAGE
ACCESS TIME
PROGRAMMING TIME
32 UNIFORM 64 KWord/128KByte MEMORY
BLOCKS
ENHANCED SECURITY
PROGRAM and ERASE SUSPEND
128 bit PROTECTION REGISTER
COMMON FLASH INTERFACE
100, 000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
PACKAGES
V
Erase and Read operations
Random Read 90ns,110ns
Page Mode Read 90ns/25ns, 110ns/25ns
16 Word Write Buffer
12 s Word effective programming time
Block Protection/ Unprotection
V
128 bit Protection Register with 64 bit
Unique Code in OTP area
Manufacturer Code: 0020h
Device Code M58LW032D: 0016h
Compliant with Lead-Free Soldering
Processes
Lead-Free Versions
DD
PEN
= V
signal for Program Erase Enable
DDQ
= 2.7 to 3.6V for Program,
32 Mbit (4Mb x8, 2Mb x16, Uniform Block)
Figure 1. Packages
3V Supply Flash Memory
TSOP56 (N)
14 x 20 mm
TBGA64 (ZA)
10 x 13 mm
TBGA
M58LW032D
1/50

Related parts for M58LW032D110N6

M58LW032D110N6 Summary of contents

Page 1

... Random Read 90ns,110ns – Page Mode Read 90ns/25ns, 110ns/25ns I PROGRAMMING TIME – 16 Word Write Buffer – Word effective programming time I 32 UNIFORM 64 KWord/128KByte MEMORY BLOCKS I ENHANCED SECURITY – Block Protection/ Unprotection – V signal for Program Erase Enable PEN – 128 bit Protection Register with 64 bit ...

Page 2

... BUS OPERATIONS Bus Read Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output Disable Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 READ MODES COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read Query Command Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/ PEN ...

Page 3

... Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Configure STS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 6. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Word-Wide Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 8. Byte-Wide Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 9. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 19 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program/Erase Controller Status (SR7) ...

Page 4

M58LW032D PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 5

... These operations can be per- formed using a single low voltage (2.7V to 3.6V) core supply. The memory is divided into 32 blocks of 1Mbit that can be erased independently possible to preserve valid data while old data is erased. Pro- gram and Erase commands are written to the Command Interface of the memory ...

Page 6

M58LW032D Figure 2. Logic Diagram DDQ 22 A0-A21 V PEN BYTE W M58LW032D SSQ 6/50 Table 1. Signal Names A0 A1-A21 BYTE DQ0-DQ15 DQ0-DQ15 ...

Page 7

Figure 3. TSOP56 Connections A21 A20 A19 A18 A17 A16 V DD A15 A14 A13 A12 M58LW032D V PEN A11 A10 ...

Page 8

M58LW032D Figure 4. TBGA64 Connections (Top view through package DQ8 F BYTE 8/ PEN A13 ...

Page 9

Figure 5. Block Addresses Byte (x8) Bus Width 3FFFFFh 1 Mbit or 128 KBytes 3E0000h 3DFFFFh 1 Mbit or 128 KBytes 3C0000h 03FFFFh 1 Mbit or 128 KBytes 020000h 01FFFFh 1 Mbit or 128 KBytes 000000h Note: Also see APPENDIX ...

Page 10

... IL until the completion of the Reset/Power-Down BH, pulse. After Reset/Power-Down goes High, V memory will be ready for Bus Read and Bus Write operations after t during a reset, see Ready/Busy Output section application recommended to associate Reset/Power-Down pin, RP, with the reset signal of the microprocessor. Otherwise reset opera- ...

Page 11

... Program/Erase Controller operations, other- wise the operations is not guaranteed to succeed and data may become corrupt. V Supply Voltage. V provides the power DD DD supply to the internal core of the memory device the main power supply for all operations (Read, Program and Erase). Table 2. Device Enable ...

Page 12

... On Power-up or after a Hardware Reset the mem- ory defaults to Read Array mode (Page Read). Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations are used to out- put the contents of the Memory Array, the Elec- tronic Signature, the Status Register, the Common Flash Interface and the Block Protection Status ...

Page 13

... Random Read (where each Bus Read oper- ation accesses a different Page) and Page Read. In Page Read mode a Page of data is internally read and stored in a Page Buffer. Each memory page Words or 8 Bytes and has the same A3-A21 mode only A0, A1 and A2 may change, in x16 mode only A1 and A2 may change ...

Page 14

... Word/Byte Program Command. The B., Tables Byte Program command is used to program a sin- gle Word or Byte in the memory array. Two Bus Write operations are required to issue the com- mand; the first write cycle sets up the Word Pro- gram command, the second write cycle latches the address and data to be programmed, and starts the Program/Erase Controller ...

Page 15

... Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the oper- ation without affecting the data in the memory ar- ray. The Status Register should be cleared before re-issuing the command. If the block being programmed is protected an er- ...

Page 16

... Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Block Protect operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Block Protection times are given in Table 9 ...

Page 17

... CC CFI. Description The STS pin is Low during Program and Erase operations and high impedance when the memory is ready for any Read, Program or Erase operation. Supplies a system interrupt pulse at the end of a Block Erase operation. Supplies a system interrupt pulse at the end of a Program operation. ...

Page 18

... Note: 1. SBA is the Start Base Address of each block, PRD is Protection Register Data. 2. Base Address, refer to Figure not used in Read Electronic Signature in either x8 or x16 mode. The data is always presented on the lower byte in x16 mode. Figure 6. Protection Register Memory Map WORD ADDRESS 88h ...

Page 19

Table 8. Byte-Wide Read Protection Register Word Use Lock Factory, User Lock Factory, User 0 Factory (Unique ID) 1 Factory (Unique ID) 2 Factory (Unique ID) 3 Factory (Unique ID) 4 Factory (Unique ID) 5 Factory (Unique ID) 6 Factory ...

Page 20

... When a Program/Erase Resume command is is- sued the Erase Suspend Status bit returns Low. Erase Status (SR5). The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. The ...

Page 21

... When the Program Suspend Status bit is Low the Program/Erase Controller is active or has OL completed its operation; when the bit is High Program/Erase Suspend command has been is- sued and the memory is waiting for a Program Erase Resume command. When a Program/Erase Resume command is is- sued the Program Suspend Status bit returns Low. ...

Page 22

M58LW032D Table 10. Status Register Bits OPERATION Program/Erase Controller active Write Buffer not ready Write Buffer ready Write Buffer ready in Erase Suspend Program suspended Program suspended in Erase Suspend Program/Block Protect completed successfully Program completed successfully in Erase Suspend ...

Page 23

... European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. Maximum one output short-circuited at a time and for no longer than 1 second. Ta- not implied. Exposure to Absolute Maximum Rat- ing conditions for extended periods may affect de- vice reliability. STMicroelectronics SURE Program and other rel- evant quality documents. Parameter M58LW032D Refer also to ...

Page 24

M58LW032D DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC characteristics Tables that follow, are de- rived from tests ...

Page 25

Table 14. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Random Read Supply Current (Page Read) DDO I Supply Current (Standby) DD1 I Supply Current (Auto Low-Power) DD5 I ...

Page 26

M58LW032D Figure 9. Bus Read AC Waveforms A0-A21 (1) E2, E1 (2) BYTE DQ0-DQ15 Note Device Disabled (first edge details. 2. BYTE can be Low or High. Table ...

Page 27

Figure 10. Page Read AC Waveforms A1-A2 A3-A21 (1) E2, E1 DQ0-DQ15 Note Device Disabled (first edge details. Table 16. Page Read AC Characteristics Symbol Parameter t Address ...

Page 28

M58LW032D Figure 11. Write AC Waveform, Write Enable Controlled A0-A21 (1) E2, E1, E0 tELWL G tGHWL W DQ0-DQ15 STS (Ready/Busy mode) V PEN Note Device Disabled (first edge details. ...

Page 29

Figure 12. Write AC Waveforms, Chip Enable Controlled A0-A21 W tWLEL G tGHEL (1) E2, E1, E0 DQ0-DQ15 STS (Ready/Busy mode) V PEN Note Device Disabled (first edge details. Table ...

Page 30

M58LW032D Figure 13. Reset, Power-Down and Power-Up AC Waveform W (1) E2, E1 DQ0-DQ15 tPHQV STS (Ready/Busy mode DDQ Note Device Disabled (first edge of E0 E2), ...

Page 31

PACKAGE MECHANICAL Figure 14. TSOP56 - 56 lead Plastic Thin Small Outline mm, Package Outline 1 N/2 TSOP-b Note: Drawing is not to scale. Table 20. TSOP56 - 56 lead Plastic Thin Small Outline ...

Page 32

M58LW032D Figure 15. TBGA64 - 10x13mm ball array 1mm pitch, Package Outline BALL "A1" A Note: Drawing is not to scale. Table 21. TBGA64 - 10x13mm ball array ...

Page 33

... E = Lead-free and RoHS Package, Standard Packing F = Lead-free and RoHS Package, Tape & Reel Packing Note: Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you ...

Page 34

M58LW032D APPENDIX A. BLOCK ADDRESS TABLE Table 23. Block Addresses Block Address Range Number (x8 Bus Width) 32 3E0000h-3FFFFFh 31 3C0000h-3DFFFFh 30 3A0000h-3BFFFFh 29 380000h-39FFFFh 28 360000h-37FFFFh 27 340000h-35FFFFh 26 320000h-33FFFFh 25 300000h-31FFFFh 24 2E0000h-2FFFFFh 23 2C0000h-2DFFFFh 22 2A0000h-2BFFFFh 21 ...

Page 35

... APPENDIX B. COMMON FLASH INTERFACE - CFI The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory ...

Page 36

... Not Available , otherwise 00h will be output. IL Data n 16h n where 2 is number of bytes memory Size 02h Device Interface 00h Organization Sync./Async. 05h Maximum number of bytes in Write Buffer, 2 00h 01h Bit7-0 = number of Erase Block Regions in device 1Fh Number (n-1) of Erase Blocks of identical size ...

Page 37

Table 28. Block Status Register Address bit0 (1,2) (BA+2)h bit1 bit7-2 Note specifies the block address location, A21-A17 mode, A0 must be set Not Supported. Table 29. Extended Query information Address (2) ...

Page 38

M58LW032D Address (2) offset x16 x8 (P+13)h 0044h 88h (P+14)h 0045h 8Ah (P+15)h 0046h 8Ch Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in ...

Page 39

APPENDIX C. FLOW CHARTS Figure 16. Write to Buffer and Program Flowchart and Pseudo Code Note 1: N+1 is number of Words to be programmed Note 2: Next Program Address must have same A5-A21. Note 3: A full Status Register ...

Page 40

... Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while Program completed Read Memory Array Command: – write FFh – one or more data reads from other blocks Program Erase Resume Command: – write D0h to resume programming – if the program operation completed then this is not necessary ...

Page 41

... Erase to Protected Block Error M58LW032D Erase command: – write 20h – write D0h to Block Address (A12-A17) (memory enters read Status Register after the Erase command) do: – read status register – if Program/Erase Suspend command given execute suspend erase loop while SR7 = 1 If SR3 = 1, V PEN invalid error: – ...

Page 42

... Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while Erase completed Read Memory Array command: – write FFh – one or more data reads from other blocks Program/Erase Resume command: – write D0h to resume the Erase operation – ...

Page 43

... Block Adress – write 01h, Block Adress do: – read status register while SR7 = 1 If SR3 = 1, V PEN Invalid Error If SR4 = 1, SR5 = 1 Invalid Command Sequence Error If SR4 = 1, Block Protect Error Read Memory Array Command: – write FFh AI06157b 43/50 ...

Page 44

... Blocks Unprotect Command – write 60h, Block Adress – write D0h, Block Adress do: – read status register while SR7 = 1 If SR3 = 1, V PEN Invalid Error If SR4 = 1, SR5 = 1 Invalid Command Sequence Error If SR5 = 1, Blocks Unprotect Error Read Memory Array Command: – write FFh AI06158b ...

Page 45

... Protection Register Address, Protection Register Data do: – read status register while SR7 = 1 If SR3 = 1, SR4 = 1 V PEN Invalid Error If SR1 = 0, SR4 = 1 Protection Register Program Error If SR1 = 1, SR4 = 1 Program Error due to Protection Register Protection Read Memory Array Command: – write FFh AI06159b 45/50 ...

Page 46

M58LW032D Figure 23. Command Interface and Program Erase Controller Flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ 98h SIGNATURE YES CFI QUERY B Note 1. The Erase command (20h) can only be issued if the flash is not ...

Page 47

Figure 24. Command Interface and Program Erase Controller Flowchart (b) WAIT FOR COMMAND WRITE READ STATUS READ SIGNATURE CFI QUERY PROGRAM BUFFER LOAD NO PROGRAM D0h COMMAND ERROR YES c B READ STATUS READ ARRAY YES NO FFh NO YES ...

Page 48

M58LW032D Figure 25. Command Interface and Program Erase Controller Flowchart (c). WAIT FOR COMMAND WRITE READ STATUS READ SIGNATURE CFI QUERY READ ARRAY 48/50 B YES READ STATUS READ ARRAY YES NO FFh NO YES PROGRAM SUSPENDED YES YES 70h ...

Page 49

REVISION HISTORY Table 30. Document Revision History Date Version 04-Jun-2002 -01 First Issue Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot. ...

Page 50

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...

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