M58LW032D110N6 STMicroelectronics, M58LW032D110N6 Datasheet - Page 12

• Manufacturer Part Number: M58LW032D110N6
• Description: IC FLASH 32MBIT 110NS 56TSOP
• Manufacturer: STMicroelectronics

Specifications of M58LW032D110N6

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 110ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1725

M58LW032D
BUS OPERATIONS
There are five standard bus operations that control
the memory. Each of these is described in this
section, see
mary.
On Power-up or after a Hardware Reset the mem-
ory defaults to Read Array mode (Page Read).
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read. Bus Read operations are used to out-
put the contents of the Memory Array, the Elec-
tronic Signature, the Status Register, the Common
Flash Interface and the Block Protection Status.
A valid bus operation involves setting the desired
address on the Address inputs, enabling the de-
vice (refer to
Low signal, V
Write Enable High, V
the previous command written to the memory (see
Command Interface section).
See
ble 15., Bus Read AC
of when the output becomes valid.
Bus Write. Bus Write operations write Com-
mands to the memory or latch addresses and input
data to be programmed.
A valid Bus Write operation begins by setting the
desired address on the Address Inputs and en-
abling the device (refer to Chip Enable section).
Table 3. Bus Operations
Note: 1. DQ8-DQ15 are High Z in x8 mode.
12/50
Figure 9., Bus Read AC
2. X = Don’t Care V
Bus Operation
Output Disable
Power-Down
Bus Read
Bus Write
Standby
Table 3., Bus
Table 2., Device
IL
, to Output Enable and keeping
IL
IH
or V
. The data read depends on
Characteristics., for details
IH
.
Operations, for a sum-
E0, E1
or E2
Waveforms, and
V
V
V
V
X
Enable), applying a
IH
IL
IL
IL
V
V
V
G
X
X
IH
IH
IL
Ta-
V
V
V
W
X
X
IH
IH
IL
The Address Inputs are latched by the Command
Interface on the rising edge of Write Enable or the
first edge of E0, E1 or E2 that disables the device
(refer to
The Data Input/Outputs are latched by the Com-
mand Interface on the rising edge of Write Enable
or the first edge of E0, E1 or E2 that disables the
device whichever occurs first. Output Enable must
remain High, V
See Figures 11, and 12, Write AC Waveforms, and
Tables
trolled Write AC Characteristics, for details of the
timing requirements.
Output Disable. The Data Inputs/Outputs are
high impedance when the Output Enable is at V
Power-Down. The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, I
independent of Chip Enable, Output Enable or
Write Enable.
Standby. Standby disables most of the internal
circuitry, allowing a substantial reduction of the
current consumption. The memory is in standby
when Chip Enable is at V
tion is reduced to the standby level I
outputs are set to high impedance, independently
of the Output Enable or Write Enable inputs.
If Chip Enable switches to V
erase operation, the device enters Standby mode
when finished.
RP
V
V
V
V
V
IH
IH
IH
IH
IL
DD2
17
Table 2., Device
, and the outputs are high impedance,
and 18, Write and Chip Enable Con-
A1-A21 (x16)
A0-A21 (x8)
IH
Address
Address
, during the Bus Write operation.
X
X
X
IH
Enable).
. The power consump-
IH
during a program or
DQ0-DQ15 (x16)
DQ0-DQ7 (x8)
Data Output
Data Input
High Z
High Z
High Z
DD1
and the
(1)
IH
.