TC58V64BFT(F) Toshiba, TC58V64BFT(F) Datasheet
TC58V64BFT(F)
Specifications of TC58V64BFT(F)
Related parts for TC58V64BFT(F)
TC58V64BFT(F) Summary of contents
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... It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property ...
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... Status register Address register Command register Control HV generator RATING PARAMETER CONDITION OUT TC58V64BFT Column buffer Column decoder Data register Sense amp Memory cell array VALUE - 0.6 to 4.6 - 0.6 to 4 £ 4 0.3 260 - 55 to 150 MIN MAX = 0 V ¾ ¾ 10 2001-10-24 2/33 ...
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VALID BLOCKS (1) SYMBOL N Number of Valid Blocks VB (1) The TC58V64B occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document. RECOMMENDED DC OPERATING CONDITIONS SYMBOL V Power Supply Voltage CC V High ...
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... WE High to CE Low WHC t WE High to RE Low WHR t ALE Low to RE Low (ID Read) AR1 t CE Low to RE Low (ID Read Memory Cell Array to Starting Address High to Busy WB t ALE Low to RE Low (Read Cycle) AR2 t RE Last Clock Rising Edge to Busy (in Sequential Read ...
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Note: (1) CE High to Ready time depends on the pull-up resistor tied to the (Refer to Application Note (8) toward the end of this document.) (2) Sequential Read is terminated when t is less than 30 ns ...
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TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O1 to I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE I/O1 to I/O8 Setup Time CLH t ...
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Address Input Cycle Timing Diagram t CLS CLE ALS ALE I/O1 to I/O8 Data Input Cycle Timing Diagram CLE CE t ALS ALE WE I/ ...
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Serial Read Cycle Timing Diagram REA I/ Status Read Cycle Timing Diagram CLE t CLS I/O1 to I/O8 RY ...
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Read Cycle (1) Timing Diagram CLE t t CLS CLH ALH ALS ALE I/O1 00H I/O8 Column address N * ...
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Read Cycle (2) Timing Diagram CLE t t CLS CLH ALH ALE I/O1 01H to I/ Read Operation using 01H Command N: 0 ...
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Sequential Read (1) Timing Diagram CLE CE WE ALE RE I/O1 00H A16 A17toA22 to I/O8 Column address Sequential Read (2) Timing Diagram CLE CE WE ALE RE I/O1 01H A0 ...
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Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 50H A16 A17toA22 to I/O8 Column address Page t 512 + 512 + 512 + R address ...
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Auto-Program Operation Timing Diagram t CLS CLE t t CLS CLH ALH t ALS ALE I/O1 80H ...
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ID Read Operation Timing Diagram CLE t CLS t CLS ALH ALS ALE I/O1 90H to I/ ALH AR1 ...
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... PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs are configured as shown in Figure 1. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE signal while CLE is High ...
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... The device does not go into a low-power Standby mode when CE goes High during Busy state of a Program or Erase operation. I/O1 A page consists of 528 bytes in which 512 bytes are used for main memory storage and 16 bytes are for redundancy I/O8 or for other uses. 1 page = 528 bytes 16 pages 1 block = 528 bytes ´ ...
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Table 3. Command table (HEX) First Cycle Serial Data Input 80 Read Mode (1) 00 Read Mode (2) 01 Read Mode (3) 50 Reset FF Auto Program 10 Auto Block Erase 60 Status Read 70 ID Read 90 Once the ...
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DEVICE OPERATION Read Mode (1) Read mode (1) is set when a 00H command is issued to the Command register. Refer to Figure 3 below for timing details and the block diagram. CLE CE WE ALE ...
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... Column address 527 on the last page. Busy Addresses bits A0~A3 are used to set the start pointer for the redundant memory cells, while A4~A7 are ignored. 527 Once a 50H command has been issued, the pointer moves to the redundant cell locations and only those 16 cells can be addressed, regardless of the value of the A4-to-A7 address ...
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Status Read The device automatically implements the execution and verification of the Program and Erase operations. The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail Program or Erase operation, ...
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Auto Page Program The device carries out an Automatic Page Program operation when it receives a “10H” Program command after the address and data have been input. The sequence of command, address and data input is shown below. (Refer to ...
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Reset The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The response to an “FFH” Reset command ...
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ID Read The TC58V64B contains ID codes which identify the device type and the manufacturer. The ID codes can be read out under the following timing conditions: CLE CE WE ALE RE I/O 90H 00 ID Read command Address 00 ...
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APPLICATION NOTES AND COMMENTS (1) Power-on/off sequence: The WP signal is useful for protecting against data corruption at power-on/off. The following timing sequence is necessary. The WP signal may be negated any time after the V power up sequence. 2.7 ...
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Status Read during a Read operation 00 command Address N The device status can be read out by inputting the Status Read command “70H” in Read mode. Once the device has been set ...
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Pointer control for “00H”, “01H” and “50H” The device has three Read modes which set the destination of the pointer. Table 7 shows the destination of the pointer, and Figure block diagram of their operations. Table ...
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termination for the Ready/Busy pin ( A pull-up resistor needs to be used for termination because the circuit Device V SS Figure 21. This data may vary from device to device. ...
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Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable ...
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When four address cycles are input Although the device may read in a fourth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H, 50H Internal read operation starts when ...
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Several programming cycles on the same page (Partial Page Program) A page can be divided into segments. Each segment can be programmed individually as follows: 1st programming Data Pattern 1 2nd programming All 1s 5th programming ...
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Invalid blocks (bad blocks) The device contains unusable blocks. Therefore, at the time of use, please check whether a block is bad and do not use these bad blocks. Bad Block Bad Block Figure 26. Bad Block Test Flow ...
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... Block Replacement Program Error occurs Buffer memory Erase When an error occurs in an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). DETECTION AND COUNTERMEASURE SEQUENCE Status Read after Erase ® Block Replacement Status Read after Program ® ...
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Package Dimensions Weight: 0.48 g (typ.) TC58V64BFT 2001-10-24 33/33 ...