TC58128AFT Toshiba, TC58128AFT Datasheet
TC58128AFT
Specifications of TC58128AFT
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TC58128AFT Summary of contents
Page 1
... I/O8 WE Write enable 43 I/O7 42 I/O6 RE Read enable 41 I/ CLE Command latch enable ALE Address latch enable Write protect Ready/Busy I/O4 GND Ground input 31 I/O3 30 I/O2 29 I/O1 V Power supply Ground TC58128AFT min 10 mA typ typ typ. 100 µA 000707EBA1 2001-05-30 1/33 ...
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... This parameter is periodically sampled and is not tested for every device. Status register Address register Command register Control HV generator RATING PARAMETER CONDITION OUT TC58128AFT Column buffer Column decoder Data register Sense amp Memory cell array VALUE −0.6 to 4.6 −0.6 to 4.6 −0 0.3 V (≤ 4 ...
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... IL OUT cycle = cycle = cycle = cycle − 0 −400 µ 2 0 pin V OL TC58128AFT MIN TYP. MAX 1004 1024 MIN TYP. MAX 2.7 3.3 3.6 + 0.3 2 −0.3* 0.8 MIN TYP. MAX ±10 ± ...
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... CE High to Ready (When interrupted Read Mode) CRY t Device Reset Time (Read/Program/Erase) RST AC TEST CONDITIONS PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load PARAMETER TC58128AFT MIN MAX UNIT ...
Page 5
... Refer to Application Note (12) toward the end of this document. is greater than or equal to 100 ns. If the delay CEH / BY signal stays Ready. t CEH 526 527 A Busy MIN 200 to 300 TC58128AFT pin. ≥ 100 → Busy signal is not output CRY ( 0° to 70° TYP ...
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... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O1 to I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE I/O1 to I/O8 Setup Time CLH ALH TC58128AFT Hold Time 2001-05-30 6/33 ...
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... Address Input Cycle Timing Diagram t CLS CLE ALS ALE I/O1 to I/O8 Data Input Cycle Timing Diagram CLE CE t ALS ALE WE I/ A16 TC58128AFT ALH A17 to A23 : CLH 527 2001-05-30 7/33 ...
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... Serial Read Cycle Timing Diagram REA I/ Status Read Cycle Timing Diagram CLE t CLS I/ 70H represents the hexadecimal number REH RHZ REA RHZ t CLS t CLH WHC CSTO t WHR 70H* TC58128AFT CHZ REA RHZ t CHZ RSTO RHZ Status output : 2001-05-30 8/33 ...
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... ALH ALS ALE I/O1 00H I/O8 Column address Read Operation using 00H Command 255 ALH AR2 A16 A17toA23 ALH AR2 A16 A17toA23 TC58128AFT REA OUT OUT OUT OUT 527 : CHZ REA RHZ OUT OUT OUT 2001-05-30 9/33 t CEH t CRY t RB ...
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... DS DH I/O1 50H to I/ Read Operation using 50H Command N: 0 to15 t ALS ALH A16 A17toA23 Column address N* t ALS ALH A16 A17toA23 Column address N* TC58128AFT t AR2 REA OUT OUT OUT 256 + M 256 + 527 : AR2 REA OUT OUT OUT 512 + M 512 + 527 ...
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... Column address Sequential Read (2) Timing Diagram CLE CE WE ALE RE I/O1 01H A16 A17toA23 to I/O8 Column address Page t R address M Page M access Page t 256 + 256 + 256 + R address Page M access TC58128AFT 527 527 t R Page access : 527 527 t R Page access : 2001-05-30 11/33 ...
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... Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 50H A16 A17toA23 to I/O8 Column address Page t 512 + 512 + 512 + R address Page M access TC58128AFT 527 512 513 514 527 t R Page access : 2001-05-30 12/33 ...
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... Auto Block Erase Setup command t ALH t ALS not input data while data is being output ALH WB D0H Erase Start command : not input data while data is being output TC58128AFT t PROG 10H 70H 527 BERASE Status 70H output Status Read Busy command 2001-05-30 13/ Status output ...
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... ID Read Operation Timing Diagram CLE t CLS t CLS ALH ALS ALE I/O1 90H to I/ ALH AR1 t REAID 00 98H Address Maker code input TC58128AFT t REAID 73H Device code : 2001-05-30 14/33 ...
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... H) after completion of the operation. The output buffer for this signal is an open drain GND CLE 16 ALE Figure 1. Pinout L), such as during a Program or Erase operation, and after the falling edge REA TC58128AFT I/O8 43 I/O7 42 I/ I/O4 31 I/O3 30 I/ signal is in 2001-05-30 15/33 ...
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... An address is read in via the I/O port over three consecutive clock cycles, as shown in Table 1. 8I/O I/O6 I/O5 I/O4 I/O3 I/ A14 A13 A12 A11 A10 A22 A21 A20 A19 A18 CLE ALE TC58128AFT I/O1 A0~A7: Column address A9~A23: Page address A0 A14~A23: Block address A9 A9~A13: NAND address in block A17 2001-05-30 16/ ...
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... Output Deselect L Standby Second Cycle Acceptable while Busy D0 ALE TC58128AFT HEX data bit assignment (Example) Serial data input: 80H I/ I/O1 I/O1~I/O8 Power L Data output Active H High impedance Active * High impedance Standby 2001-05-30 17/33 ...
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... The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer set after column address 256, use Read mode (2). However, for a Sequential Read, output of the next page starts Cell array from column address 0. TC58128AFT 2001-05-30 18/33 ...
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... A4-to-A7 address. (An 00H command is necessary to move the pointer back to the 0-to-511 main memory cell location.) Data output t R Busy 527 (01H) A Sequential Read (2) TC58128AFT Data output Busy Busy (50H) 512 527 A Sequential Read (3) ...
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... Device Device 2 3 Busy 70H Status on Device 1 Figure 6. Status Read timing application example pin signals from multiple devices are wired together as shown in the TC58128AFT The Pass/Fail status on I/O1 is only valid when the device is in the Ready state Device Device Status on Device N ...
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... After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. D0 Busy TC58128AFT Pass 70 I/O Status Read Fail command ...
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... The second FF (max 10 µs) t RST (max 6 µs) t RST command is invalid, but the third TC58128AFT Figure 8. 00 Figure 9. 00 (max 500 µs) RST Figure 10. 00 Figure 11. I/O status: Pass/Fail → Pass Ready/Busy → Ready I/O status: Ready/Busy → Busy Figure 12. ( command is valid ...
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... Table 6. ID Codes read out by ID read command 90H I/O8 I/O7 Maker code 1 0 Device code AR1 t REAID 98H Maker code , t and t refer to the AC Characteristics. REAID CR AR1 Figure 13. ID Read timing I/O6 I/O5 I/O4 I/ TC58128AFT 73H Device code I/O2 I/O1 Hex Data 0 0 98H 1 1 73H 2001-05-30 23/33 ...
Page 24
... Programming cannot be executed. “10H” or “FFH” reaches 2.5 V and CE signal is kept high Operation Figure 15. Power-on/off Sequence becomes 2 recommends starting access after about CC FF Reset Figure 16. 10 For this operation the “FFH” command is needed. TC58128AFT Don’t care V IL 2001-05-30 24/33 ...
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... Read mode. In this case, data output starts automatically from address N and address input is unnecessary Ex.) Random page program (Prohibition) DATA IN: Data (1) Page 0 (1) Page 1 (2) (3) Page 2 Page 15 Page 31 Figure 17. page programming within a block 70 Status Read command input Figure 18. TC58128AFT Data (32) Data register (2) (16) (3) (1) (32) 00 [A] Status Read Status output 2001-05-30 25/33 ...
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... C area C area Add Start point B area A area Add DIN Start point C Area Add DIN Start point B Area Figure 20. Example of How to Set the Pointer TC58128AFT 255 256 511 512 A B Pointer control Figure 19. Pointer control 50H Add Start point C area 00H Add ...
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... This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value Ready 1.5 µs 1.0 µ 0.5 µ KΩ TC58128AFT buffer consists of an open drain 3.0 V Busy 1 3 25° 100 KΩ 3 KΩ 4 KΩ ...
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... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE DIN (100 ns min) WW Enable Erasing WE DIN (100 ns min) WW Disable Erasing WE DIN (100 ns min TC58128AFT 2001-05-30 28/33 ...
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... Although the device may read in a fourth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H, 50H Internal read operation starts when WE goes High in the third cycle. Program operation CLE CE WE ALE I/O 80H Address input Figure 22. Address input Ignored Figure 23. TC58128AFT Ignored Data input 2001-05-30 29/33 ...
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... Busy state. (Refer to Figure 25.) I/O 00H/01H/50H Hence the RE clock input must start after the address input. All 1s Data Pattern 2 All 1s Data Pattern 2 Figure 24. Address input Figure 25. TC58128AFT All 1s Data Pattern 3 Data Pattern 3 2001-05-30 30/33 ...
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... The number of valid blocks at the time of shipment is as follows: MIN Valid (Good) Block Number 1004 Read Check: to verify all pages in the block Start Block Fail Read Check Pass Block No. = 1024 Yes End Figure 27 TC58128AFT TYP. MAX UNIT 1024 Block with FF (Hex) Bad Block *1 2001-05-30 31/33 ...
Page 32
... Block Verify after Program → Retry (2) ECC When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, Block A prevent further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block B Figure 28. TC58128AFT 2001-05-30 32/33 ...
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... Package Dimensions Weight: 0.53 g (typ.) TC58128AFT 2001-05-30 33/33 ...