MD4832-D512-V3Q18-X/Y SanDisk, MD4832-D512-V3Q18-X/Y Datasheet - Page 43

• Manufacturer Part Number: MD4832-D512-V3Q18-X/Y
• Description: IC MDOC G3 512MB 85-FBGA
• Manufacturer: SanDisk

Specifications of MD4832-D512-V3Q18-X/Y

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 512M (64M x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 585-1140

2.
3.
4.
5. If an ECC error is detected, an interrupt is generated (IRQ# signal asserted), the transfer of data
6.
Notes: 1. Mobile DiskOnChip G3 generates a DMA request (DMARQ# signal asserted) after the
4.3
When using MultiBurst mode and DMA operation together, and an interrupt is generated (IRQ#
signal asserted), the Download Status register cannot be polled, as it will not comply with the
MultiBurst mode timing specification. The following sequence is therefore required to respond to
an interrupt request while in MultiBurst mode:
•
•
4.4
In order to provide faster read access time, Mobile DiskOnChip G3 can be configured for Turbo
operation by enabling the D[15:0] output buffers immediately after the assertion of OE# and CE#.
Enter Turbo operation by setting the TURBO bit in the Output Control register. For timing
specifications for Turbo operation, see Section 10.3.
Since the read access time for the Programmable Boot Block is slower than the read access time for
the registers, bus contention may occur when reading from the Programmable Boot Block during
system boot. It is therefore not recommended to use Turbo operation during boot, but only after the
system is up and running and Mobile DiskOnChip G3 is being used as a flash disk.
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Set the bits in the Interrupt Control register (see Section 7) to enable interrupts on an ECC error
and at the end of the DMA operation.
Write to the DMA Control register[0] to set the DMA_EN bit, the EDGE bit and the number of
sectors (SECTOR_COUNT bit) to be transferred to the host. At this point, Mobile DiskOnChip
G3 generates a DMA request to indicate to the host that it is ready to transfer data.
The host DMA controller reads one sector (512 bytes) of data from Mobile DiskOnChip G3.
is halted and control is returned to the host. If no ECC error is detected, a DMA request is
initiated (DMARQ# signal asserted) and the next sector is read by the host.
The process continues until the last sector is read, after which Mobile DiskOnChip G3
generates an interrupt (IRQ# signal asserted) to indicate that it has transferred the last byte.
Perform 7 write cycles to the NOP register.
Turn off MultiBurst mode by writing to the MultiBurst Mode Control register.
2. DMA operation may be aborted after transferring each 512-byte block (step 4) by
Combined MultiBurst Mode and DMA Operation
Turbo Operation
last byte is read. It may therefore be necessary to clear the final DMA request from the
DMA controller.
clearing the DMA_EN bit in the DMA Control register[0].
Preliminary Data Sheet, Rev. 1.1
Mobile DiskOnChip G3
91-SR-011-05-8L