MD5811-D256-V3Q18 SanDisk, MD5811-D256-V3Q18 Datasheet - Page 47
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MD5811-D256-V3Q18
Manufacturer Part Number
MD5811-D256-V3Q18
Description
IC MDOC P3 256MB 48-TSOP
Manufacturer
SanDisk
Datasheet
1.MD5811-D256-V3Q18-P.pdf
(86 pages)
Specifications of MD5811-D256-V3Q18
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
256M (32M x 8)
Speed
55ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MD5811-D256-V3Q18-P
Manufacturer:
M-SYSTEMS
Quantity:
20 000
Company:
Part Number:
MD5811-D256-V3Q18-P/Y
Manufacturer:
PULSE
Quantity:
47
Part Number:
MD5811-D256-V3Q18-P/Y
Manufacturer:
M-SYSTEMS
Quantity:
20 000
Company:
Part Number:
MD5811-D256-V3Q18-X
Manufacturer:
M-SYSTEMS
Quantity:
19 491
Part Number:
MD5811-D256-V3Q18-X
Manufacturer:
M-SYSTEMS
Quantity:
20 000
Company:
Part Number:
MD5811-D256-V3Q18/Y
Manufacturer:
MOTO
Quantity:
18 911
8.6
Description:
Address (hex): 1006
Type:
Reset Value:
44
Bit No.
7-0
Bus Lock Register
D[7:0]: CPU Control value
This register provides a mechanism for a CPU to request and hold sole access
rights to Mobile DiskOnChip P3 in multiprocessor applications.
The following algorithm must be implemented to ensure that only one CPU at a
time accesses Mobile DiskOnChip P3:
1.
2.
3.
4.
Read/Write
0
Before beginning an indivisible operation sequence (e.g. reading/writing a
sector to the DiskOnChip), the value of this register is read. If it is non-zero,
then it must continue to be polled until it becomes zero.
Once the value read is zero, a non-zero value unique to each CPU is written
to this register to indicate to other CPUs that the device is in use.
The value written must then be confirmed. If the register returns the same
value that was written, then the CPU is assured of sole access rights to
Mobile DiskOnChip P3. If it is not the same value, then another CPU has
claimed access rights to the device and the process must be repeated from
step 1.
Upon completion of the indivisible operation sequence, this register must be
set to 00H to release the lock and permit other CPUs to access the device.
Data Sheet, Rev. 0.3
Description
Mobile DiskOnChip P3
93-SR-009-8L