SDED5-004G-NCT SanDisk, SDED5-004G-NCT Datasheet

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SDED5-004G-NCT

Manufacturer Part Number
SDED5-004G-NCT
Description
IC MDOC H3 4GB FBGA
Manufacturer
SanDisk
Datasheet

Specifications of SDED5-004G-NCT

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
32G (4G x 8)
Interface
Parallel
Voltage - Supply
1.65 V ~ 1.95 V
Operating Temperature
-25°C ~ 85°C
Package / Case
115-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SDED5-004G-NCT
Manufacturer:
SanDisk
Quantity:
10 000
Part Number:
SDED5-004G-NCT
Manufacturer:
SANDISK
Quantity:
490
H
mDOC H3 is an Embedded Flash Drive (EFD)
designed for mobile handsets and consumer
electronics devices. mDOC H3 is the new
generation of SanDisk’s successful mDOC
product family, enabling tens of millions of
handsets and other mobile devices since the
year 2000.
mDOC H3 is a hybrid device combining an
embedded thin flash controller and standard
flash memory.
In addition to the high reliability and high
system performance offered by the current
mDOC family of products, mDOC H3 offers
plug-and-play integration, support for multiple
NAND technologies and more features such as
advanced power management schemes.
mDOC H3 uses advanced Multi-Level Cell
(MLC) and binary (SLC) NAND flash
technologies, enhanced by SanDisk’s
proprietary TrueFFS embedded flash
management software running as firmware on
the flash controller.
The breakthrough in performance, size, cost
and design makes mDOC H3 the ideal solution
for mobile handsets and consumer electronics
manufacturers who require easy integration,
fast time to market, high-capacity, small form
factor, high-performance and most importantly,
highly reliable storage.
© 2007 SanDisk® Corporation
IGHLIGHTS
Embedded Flash Drive (EFD) featuring Embedded TrueFFS
Flash Management Software
mDOC H3
1
mDOC H3 enables multimedia driven
applications such as music, photo, video, TV,
GPS, games, email, office and other
applications.
E
SanDisk’s proprietary TrueFFS flash
management software is now embedded within
the mDOC H3 device and runs as firmware
from the flash controller.
Embedded TrueFFS enables mDOC H3 to
fully emulate a hard disk to the host processor,
MBEDDED
Host
Host
Host
Host
Host
Host
Figure 1: TrueFFS - Legacy mDOC vs.
+
+
+
+
+
+
mDOC H3 Architecture
T
RUE
Legacy mDOC Architecture
Legacy mDOC Architecture
+
+
+
+
+
+
FFS
mDOC H3 Architecture
mDOC H3 Architecture
Controller
Controller
Controller
Controller
Controller
Controller
Flash
Flash
Flash
Flash
Flash
Flash
Data Sheet, May 2008
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+
+
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92-DS-1205-10
Flash
Flash
Flash
Flash
Flash
Flash
®

Related parts for SDED5-004G-NCT

SDED5-004G-NCT Summary of contents

Page 1

... IGHLIGHTS mDOC Embedded Flash Drive (EFD) designed for mobile handsets and consumer electronics devices. mDOC H3 is the new generation of SanDisk’s successful mDOC product family, enabling tens of millions of handsets and other mobile devices since the year 2000. mDOC hybrid device combining an embedded thin flash controller and standard flash memory ...

Page 2

Rev. 1.3 enabling read/write operations that are identical to a standard, sector-based hard drive. In addition, Embedded TrueFFS employs patented methods, such as virtual mapping, dynamic and static wear-leveling, and automatic block management to ensure high data reliability and maximize ...

Page 3

Rev. 1.3 mDOC H3 8Gb/16Gb/32Gb/64Gb - 115-ball Fine-Pitch Ball Grid Array (FBGA) 12x18mm Ball to ball compatible with mDOC G3/G4/H1 families. Enhanced performance by implementation of: Multi-plane operations DMA support Burst operation Dual Data RAM buffering Read/Write Cache Fast partition ...

Page 4

... T FFS S MBEDDED RUE TrueFFS (True Flash File System) is SanDisk’s field proven patented flash management software. TrueFFS is embedded within the mDOC H3 device, providing full Block Device functionality to the Operating System (OS) file system via either TrueFFS 7.1 (for supporting both earlier mDOC products and mDOC H3) or the DOC Driver ...

Page 5

Rev. 1 EVISION ISTORY Doc. No Revision 92-DS-1205-10 0.1 January 2006 0.2 June 2006 5 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet Date Description Preliminary version RSRVD balls left floating changed from a recommendation to a requirement ...

Page 6

Rev. 1.3 Doc. No Revision 1.0 February 2007 6 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet Date Description Ordering information modified Refer to Standard Interface as Demux Current/Power consumption numbers modified Number of partitions available changed from 10 to ...

Page 7

... Updated parameter Tcesu Add 10x14 package mechanical description Added note on ball size change of new products Ordering info section updated Added new SanDisk top marking 128KB window updated Updated DMA transfer timing diagram Remove internal pull up of #AVD signal Updated Icc max values for new ...

Page 8

Rev. 1 ABLE OF ONTENTS 1. Introduction..............................................................................................................................12 2. Product Overview ....................................................................................................................13 2.1 Product Description ..........................................................................................................13 2.2 Demux (Standard) Interface .............................................................................................14 2.2.1 9x12/10x14/12x18 FBGA Ball Diagrams ............................................................................14 2.2.2 9x12/10x14/12x18 FBGA Signal Description......................................................................16 2.2.3 System Interface .................................................................................................................19 2.3 Multiplexed Interface.........................................................................................................19 ...

Page 9

... Power Failure Management ................................................................................................36 6.3.5 Error Detection/Correction ..................................................................................................36 6.3.6 Special Features through I/O Control (IOCTL) Mechanism................................................36 6.3.7 Compatibility........................................................................................................................37 6.4 128KB Memory Window ...................................................................................................37 6.5 8KB Memory Window .......................................................................................................39 7. mDOC H3 Registers ................................................................................................................40 7.1 Definition of Terms............................................................................................................40 7.2 Reset Values ....................................................................................................................40 7.3 Registers Description........................................................................................................41 7.3.1 Paged RAM Command Register.........................................................................................41 7 ...

Page 10

Rev. 1.3 9.5 mDOC H3 Power Supply Connectivity .............................................................................51 9.6 Connecting Control Signals ..............................................................................................55 9.6.1 Demux Interface..................................................................................................................55 9.6.2 Multiplexed Interface ...........................................................................................................55 9.7 Implementing the Interrupt Mechanism ............................................................................56 9.7.1 Hardware Configuration ......................................................................................................56 9.7.2 Software Configuration........................................................................................................56 9.8 DMA and Burst Operation.................................................................................................56 9.8.1 ...

Page 11

Rev. 1.3 10.4 Mechanical Dimensions....................................................................................................79 10.4.1 mDOC H3 1Gb (128MB)/2Gb (256MB) ..............................................................................79 10.4.2 mDOC H3 4Gb (512MB)/8Gb (1GB) ..................................................................................80 10.4.3 mDOC H3 8Gb (1GB)/ 16Gb (2GB)/ 32Gb (4GB) / 64Gb (8GB)........................................81 11. Ordering Information...............................................................................................................82 12. Markings...................................................................................................................................83 12.1 mDOC H3 1Gb ...

Page 12

... Environmental, electrical, timing and product specifications Section 10: Information on ordering mDOC H3 Section 11: Marking information Section 12: For additional information on SanDisk’s flash disk products, please contact one of the offices listed on the back page. © 2007 SanDisk® Corporation mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet 12 Introduction ...

Page 13

... VERVIEW 2.1 Product Description mDOC H3 is the latest addition to SanDisk’s mDOC product family. mDOC H3, packaged in a small FBGA package and offering densities ranging from 1Gb (128MB) to 16Gb (2GB hybrid device with an embedded flash controller and high capacity flash memory. It uses advanced Flash technologies, enhanced by SanDisk’ ...

Page 14

Rev. 1.3 of these features enables mDOC H3 to implement better security schemes to protect the code and data it stores. mDOC H3 can be configured to work with either demux (standard) interface or multiplexed (MUX) interface. Using a multiplexed ...

Page 15

Rev. 1.3 9x12/10x14/12x18 FBGA Package RSRVD RSRVD D RSRVD RSRVD E A3 GPIO _ TIMER F RSRVD A 2 RSRVD RSRVD H RSRVD RSRVD ...

Page 16

... Write Enable, active low Configuration ST/PU RSRVD. This signal may be left floating or pulled up. Identification. Configuration control to support up to two chips cascaded in the same memory window. PD Chip 1: ID0 = VSS Chip 2: ID0 = VCCQ Lock, active low. When active, provides full ST hardware data protection of selected partitions ...

Page 17

Rev. 1.3 Signal Ball No. Signal Type CLK L6 DMARQ# H8 CMOS output IRQ# G9 CMOS output ST/PU/CMOS 3- SCS# G10 ST/PU/CMOS 3- SO H10 ST/PU/CMOS 3- SI J10 ST/PU/CMOS 3- SCLK K10 VCC2 D5 VCC1 E7 VCCQ K6, G4 ...

Page 18

... The following abbreviations are used Schmitt Trigger input. IN/PD – CMOS input with internal pull down resistor (77KΩ to 312KΩ; 135KΩ typical), which is enabled only when 8KB memory window is in use, ST/PU - Schmitt Trigger input with internal pull up resistor (95KΩ ...

Page 19

Rev. 1.3 2.2.3 System Interface See Figure 3 for a simplified I/O diagram of a Demux interface to mDOC H3. The power connections and capacitors in this diagram are for illustration only. For detailed recommendations regarding power connections and required ...

Page 20

Rev. 1.3 9x12/10x14/12x18 FBGA Package RSRVD D RSRVD RSRVD E VSS GPIO _ TIMER F RSRVD VSS G RSRVD VSS RSRVD VSS H RSRVD RSRVD RSRVD K RSRVD ...

Page 21

... RSRVD. This signal may be left floating or pulled up. ST Address Valid strobe. Set multiplexed interface. PD Identification. Configuration control to support up to two chips cascaded in the same memory window. Chip 1: ID0 = VSS Chip 2: ID0 = VCCQ ST Lock. Active low. When active, provides full hardware data protection of selected partitions ...

Page 22

Rev. 1.3 Signal Ball No. Signal Type ST/PU/CMOS SCS# G10 ST/PU/CMOS SO H10 ST/PU/CMOS SI J10 ST/PU/CMOS SCLK K10 VCC2 D5 VCC1 E7 VCCQ K6, G4 VCC K5 VSS D3, D4, D7, D8, E2, E3, E4 E8, E10, F2, F3, ...

Page 23

... The following abbreviations are used Schmidt Trigger input. IN/PD – CMOS input with internal pull down resistor (77KΩ to 312KΩ; 135KΩ typical), which is enabled only when the 8KB memory window is in use, ST/PU - Schmitt Trigger input with internal pull up resistor (95KΩ ...

Page 24

Rev. 1.3 For power connectivity please refer to mDOC H3 power supply connectivity in section 9.5. Figure 5: Multiplexed Interface Simplified I/O Diagram 24 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet Product Overview 92-DS-1205-10 ...

Page 25

... ECC / EDC - Error Detection and Error Correction Codes (EDC/ECC) - On-the-fly Flash error handling. • Data Buffer – 4KB Dual-Port RAM memory, used as a pipeline buffer, for enhanced data transfer rate. • Flash Agent – Provides High level Flash management functions and sequences for Flash control and error condition handling ...

Page 26

... NOR-like interface enables direct access to the Programmable Boot Block to permit XIP (Execute-In-Place) functionality during system initialization. A1-A16 address lines enable access to the mDOC H3 128KB memory window. When migrating from mDOC G3/G4/H1 without changing the PCB, thus using only A1-A12 address lines, mDOC H3 exports 8KB memory window, like in mDOC G3/G4 and H1 ...

Page 27

Rev. 1.3 3.2.3 Serial Interface The Serial interface (SPI) provides mDOC H3 a secondary interface with debug and programming capabilities. mDOC H3 SPI Interface is configured as Slave. All four combinations of clock phase (CPHA) and clock polarity (CPOL) which ...

Page 28

... Error Detection Code/Error Correction Code (EDC/ECC) Since NAND-based flash is prone to errors, it requires unique error-handling capabilities to ensure required reliability. SanDisk’s TrueFFS technology, embedded within mDOC H3, includes a powerful Error Detection Code / Error Correction Code (EDC/ECC), based on the Bose, Chaudhuri and Hocquenghem (BCH) algorithm. Both EDC and ECC are implemented in hardware to optimize performance ...

Page 29

Rev. 1 ATA ROTECTION AND 4.1.1 Read/Write-Protected partitions Data and code protection is implemented on a per-partition basis. The user can configure each partition as read protected, write protected, or read and write protected. A protected partition ...

Page 30

Rev. 1.3 4.1.4 Unique Identification (UID) Number Each mDOC H3 is assigned a 16-byte UID number. Burned onto the flash during production, the UID cannot be altered and is worldwide unique. The UID is essential for security-related applications, and can ...

Page 31

Rev. 1.3 5. DOC ODES OF Figure 7 shows the different modes of mDOC H3 device operation and the interchange between optional modes. mDOC H3 can operate in any one of five basic power modes/states: • Reset ...

Page 32

... This mode is defined as a "work mode" and is optimized for balance between power consumption and performance. Balance is achieved by setting internal clocks to predefined optimal settings. In this mode all standard operations involving the flash memory can be performed. 5.4 Standby Mode mDOC H3 enters standby mode upon device inactivity. In Standby mode the clock of most internal cores is either disconnected or reduced to a minimum ...

Page 33

Rev. 1.3 5.5 Deep Power-Down Mode While in Deep Power-Down (DPD) mode, the quiescent power dissipation of the mDOC H3 device is further reduced by disabling internal high current consumers (e.g. voltage regulators, input buffers, oscillator etc.) Entering Deep Power-Down ...

Page 34

... RUE 6.1 General Description SanDisk’s patented TrueFFS technology was designed to maximize the benefits of flash memory while overcoming inherent flash limitations that would otherwise reduce its performance, reliability and lifetime. TrueFFS emulates a hard disk making flash transactions completely transparent to the OS. In addition, since DOC Driver operates under the OS file system layer, and exports standard Block Device API completely transparent to the application ...

Page 35

... FAT, registry, etc.). Without any special handling, these pages would wear out more rapidly than other pages, reducing the lifetime of the entire flash. To overcome this inherent deficiency, Embedded TrueFFS uses SanDisk’s patented wear- leveling algorithm. This wear-leveling algorithm ensures that consecutive writes of a specific sector are not written physically to the same page in the flash ...

Page 36

... This limited application of wear-leveling would lower life expectancy significantly in cases where flash memory contains large static areas. To overcome this problem, Embedded TrueFFS forces data transfer in static areas as well as in dynamic areas, thereby applying wear-leveling to the entire media ...

Page 37

... Memory Window mDOC H3 utilizes a 128KB memory window in the CPU address space, consisting of four 32KB sections as depicted in Figure 8. The addresses described here are relative to the absolute starting address of the 128KB memory window. The 32KB Programmable Boot Block (XIP) is aliased to section 0, 2 and 3. The sections are aligned to addresses 00000H, 10000H and 18000H additionally the second half of section 1 contains the second half of the IPL ...

Page 38

... Rev. 1.3 Note: In future mDOC H3, IPL RAM size is 8KB. For backward compatibility with the memory map, each 32K window is composed of 8K IPL and 3 additional aliases. 38 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet 128K window 00000h IPL RAM (Host XIP) 08000h H3 Registers 0C000h IPL RAM – ...

Page 39

... Rev. 1.3 6.5 8KB Memory Window For the purposes of backward compatibility, mDOC H3 can present an 8KB memory window in the CPU address space, depicted in Figure 9. The addresses described here are relative to the absolute starting address of the 8KB memory window. The 2KB Programmable Boot Block (XIP) in section 0 is aligned to address 0000H. ...

Page 40

Rev. 1.3 7. DOC EGISTERS This section describes various mDOC H3 registers and their functions. Address (Hex) Address (Hex) 128KB Window 8KB Window 0030 0070 0080 9400/9422 9402/9424 9404 940C 9416 940E 9418 9410 9412 7.1 Definition ...

Page 41

Rev. 1.3 7.3 Registers Description This section describes various mDOC H3 registers and their functions. 7.3.1 Paged RAM Command Register Description: This 8-bit register is used to enable Write to other Paged RAM registers. Address (hex): 0030 (both 8KB window ...

Page 42

Rev. 1.3 7.3.3 Paged RAM Unique ID Download Register Description: Writing to this 8 bit register initiates a download of the 16-byte Unique Identification (UID) number to offset 0 of the downloadable section of the IPL RAM. After polling for ...

Page 43

Rev. 1.3 D15-D14 D13 Read/Write R R/W Bit name RFU HOLD Reset value 0 0 HOLD See section 9.8.2. LENGTH See section 9.8.2. LATENCY See section 9.8.2. WAIT_STATE See section 9.8.2. BURST_EN Enables burst mode cycles. 0: Burst mode is ...

Page 44

Rev. 1.3 WAKE_UP_SEL_BIT Selects the device wake up trigger 0: mDOC H3 CE# is the wakeup trigger. 1: Read access (CE# & OE# assertion) or write access (CE# and WE# assertion) is the wakeup trigger. 7.3.8 DPD Activation Register Description: ...

Page 45

Rev. 1.3 1: active low DMA_EN DMA enable bit: 0: DMARQ# is disabled 1: DMARQ# is enabled 7.3.10 DMA Negation Register Description: This 16-bit register controls the negation of DMARQ# signal to the host. Address (hex): 9418 (128KB window) / ...

Page 46

Rev. 1.3 7.3.12 Endian Control Register Description: This 16-bit register is used to control the swapping of the low and high data bytes when reading or writing with a 16-bit host. This provides an Endian- independent method of enabling/disabling the ...

Page 47

... OS Boot loader from its dedicated partition. SanDisk’s DOC Driver, SDK and utilities enable the construction of a proper mDOC H3 layout in order to support the boot sequence. For a complete description of these tools, refer to the DOC Driver 1 ...

Page 48

... When two mDOC H3 devices are cascaded, Paged RAM downloads occur only on the first mDOC H3 device in the cascaded configuration (device-0). For more information on booting from mDOC H3 in Paged RAM Boot mode, please contact your local SanDisk sales office. 48 Booting from mDOC H3 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet ...

Page 49

... Demux (Standard) Interface mDOC H3 uses a NOR-like interface that can easily be connected to any microprocessor bus. With a demux interface, it requires 16 address lines, 16 data lines and basic memory control signals (CE#, OE#, WE#), as shown in Figure 11 below. Typically, mDOC H3 can be mapped to any free 128KB memory space (8KB address space requires less address lines). ...

Page 50

Rev. 1.3 For power connectivity please refer to mDOC H3 power supply connectivity in section 9.5. Notes: 1. mDOC edge-sensitive device and care should be taken to prevent excessive ringing on the CE#, OE# and WE# signals. ...

Page 51

... The values listed are the minimum required values and may be increased. However any major deviations from the values specified above should be verified with SanDisk. 4. The values of capacitors listed as recommended may be modified based upon the specific behavior of the system power supply and board layout. These are bypass capacitors and they are required to minimize ripples on the power supply inputs ...

Page 52

... However, for for SDED5-AAAB-CCC devices, a 47nF capacitor will be required. 14. For the current mDOC H3 device a 0.1uF capacitor is required but it can also be operated with a 0.33uF capacitor. However, f for SDED5-AAAB-CCC devices, a 0.33uF capacitor will be required. This applies only to 1.8V Core and I/O configuration. ...

Page 53

Rev. 1.3 Figure 13: mDOC H3 power connection for 3.3v core/3.3v I/O Figure 14: mDOC H3 power connection for 3.3v core/1.8v I/O 53 Design Considerations mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet 92-DS-1205-10 ...

Page 54

Rev. 1.3 Figure 15: mDOC H3 power connection for 1.8v core/1.8v I/O 54 Design Considerations mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet 92-DS-1205-10 ...

Page 55

... OE# (Output Enable) and Write Enable (WE#) – Connect these signals to the host RD# and WR# signals, respectively. • CE# (Chip Enable) – Connect this signal to the memory address decoder. Most RISC/mobile processors include a programmable decoder to generate various Chip Select (CS) outputs for different memory zones. These CS signals can be programmed to support different wait states to accommodate mDOC H3 timing specifications ...

Page 56

Rev. 1.3 cycle made to mDOC must observe the multiplexed mode protocol. See Section 10 for more information about the related timing requirements. Please refer to Section 2.3 for ballout and signal descriptions, and to Section 10 for timing specifications ...

Page 57

Rev. 1.3 2. Level DMARQ# output is asserted while the data is available for read, or data can be accepted for write. The EDGE bit is set to 0 for this mode. The following steps are required in order to ...

Page 58

Rev. 1.3 9.8.2.1 Read Mode The LATENCY field controls the number of clock cycles between mDOC H3 sampling CE# being asserted and when the first word of data is available to be latched by the host. This number of clock ...

Page 59

Rev. 1.3 Burst CLK CE OE AVD Data Valid address Notes: 1. Note: AVD must be asserted on the following clock after the assertion of CE collision should be allowed between the AVD and OE signal. 9.8.2.2 Write ...

Page 60

Rev. 1.3 9.9 Device Cascading Up to two devices can be cascaded with no external decoding circuitry. Figure 19 illustrates the configuration required to cascade two devices on the host bus (only the relevant cascading signals are included in this ...

Page 61

Rev. 1.3 9.10 Platform-Specific Issues This section discusses hardware design issues for major embedded RISC processor families. 9.10.1 Wait State Wait states can be implemented only when mDOC H3 is designed in a bus that supports a Wait state insertion, ...

Page 62

Rev. 1.3 16-Bit (Word) Data Access Mode The mDOC bit wide device. All accesses to and from the device are 16 bit wide. mDOC H3 address lines should be connected to system host address lines, as depicted ...

Page 63

... TrueFFs 7.1 Software Development Kit (SDK) • XP utilities: o DFormat o DImage o DInfo • Documentation: o Data sheet o Application notes o Technical notes o Articles o White papers Please visit the SanDisk website (www.sandisk.com) for the most updated documentation. 63 Design Considerations mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet 92-DS-1205-10 ...

Page 64

Rev. 1.3 10 RODUCT PECIFICATIONS 10.1 Environmental Specifications 10.1.1 Operating Temperature Product Ordering Info MD2534-XXX-YY SDE-ZZ-XXXY-BBB 10.1.2 Thermal Characteristics Junction to Case (θ 10.1.3 Humidity 10% to 90% relative, non-condensing. 10.2 Electrical Specifications 10.2.1 Absolute Maximum Ratings Parameter ...

Page 65

Rev. 1.3 2. When operating mDOC H3 with separate power supplies for VCCQ/VCC/VCC1/VCC2 recommended to turn the supplies on and off simultaneously. Providing power separately (either at power-on or power-off) can cause excessive power dissipation. Damage to the ...

Page 66

Rev. 1.3 10.2.3.2 3.3V Core, 1.8V I/O Symbol Parameter VCCQ I/O power supply VCC2 Internal supply VCC Device supply VCC1 Internal supply Input High-level Voltage VIH Input Low-level Voltage VIL II Input Leakage Current IOZ Tri-State output leakage current Hysteresis ...

Page 67

Rev. 1.3 10.2.3.3 3.3V Core, 3.3V I/O Symbol Parameter VCCQ I/O power supply VCC2 Internal supply VCC Device supply VCC1 Internal supply VIH Input High-level Voltage VIL Input Low-level Voltage II Input Leakage Current IOZ Tri-State output leakage current Vhys ...

Page 68

Rev. 1.3 10.3 Timing Specifications 10.3.1 Operating Conditions Timing specifications are based on the conditions defined in Table 12. Parameter Ambient temperature (TA) Supply Voltage (VCCQ) Input fall CLK, SCS#, SI, and rise SO, SCLK time (10%- All other inputs ...

Page 69

Rev. 1.3 10.3.2 Demux Asynchronous Read Timing Figure 22: Demux Asynchronous Read Timing CE OE Tsua Address Data Figure 23: Demux Read Timing – Asynchronous Boot Mode Table 13: Demux Asynchronous Read Timing Parameters Symbol Tsua Address setup time (Figure ...

Page 70

Rev. 1.3 10.3.3 Demux Asynchronous Write Timing Figure 24: Demux Asynchronous Write Timing Table 14: Demux Asynchronous Write Timing Parameters Symbol Tasu Address setup Tah Address hold time Tdsu Data setup Tdh Data hold Tw(ceh) CE# high pulse width Tw(cel) ...

Page 71

Rev. 1.3 Table 15: Multiplexed Asynchronous Read Timing Parameters Symbol Tasu Address setup Tah Address hold Taccs Access time Tdh Data hold Tavd AVD# pulse width Tw(oel) OE# low pulse width Tw(oeh) OE# high pulse width Tavdoe AVD rising to ...

Page 72

Rev. 1.3 10.3.6 Demux Burst Read Timing Figure 27: Demux Burst Read Timing Diagram Table 17: Demux Burst Read Timing Parameters Symbol Tasu Address setup Tah Address hold Tcesu CE# setup Tacc Access time Tcyc Burst clock cycle time Tdh ...

Page 73

Rev. 1.3 10.3.7 Demux Burst Write Timing Burst CLK Tces u CE Tah Tasu Address A0 Tweh Twesu WE Data Figure 28: Demux Burst Write Timing Diagram Table 18: Demux Burst Write Timing Parameters Symbol Tasu Address setup Tah Address ...

Page 74

Rev. 1.3 10.3.8 Multiplexed Burst Read Timing Burst CLK Tcesu CE OE Tavdh Tavdsu AVD Tasu Tah Data Valid address Figure 29: Multiplexed Burst Read Timing Diagram Table 19: Multiplexed Burst Read Timing Parameters Symbol Tasu Address setup Tah Address ...

Page 75

Rev. 1.3 10.3.9 DMA Request Timing Diagram 10.3.9.1 Asynchronous Data Transfer Table 20 lists DMA request timing parameters and Figure 30 shows the DMA request timing diagram in Asynchronous data transfer. CE/OE DMARQ# Figure 30: DMA Request Timing Diagram (Asynchronous ...

Page 76

Rev. 1.3 10.3.10 SPI Timing Table 22 lists SPI slave timing parameters. Figure 32 and Figure 33 show the SPI slave timing diagram. Symbol Description tw(SCLK1) SCLK high pulse width tw(SCLK0) SCLK low pulse width tcyc(SCLK) SCLK period tsu(SI) SI ...

Page 77

... Power-Up Timing mDOC H3 is reset by assertion of the RSTIN# input. When this signal is negated, mDOC H3 initiates a download procedure from the flash memory into the internal Programmable Boot Block. During this procedure, mDOC H3 does not respond to read or write access. Host systems must therefore observe the requirements described below for initial access to mDOC H3 ...

Page 78

Rev. 1.3 Symbol T (VCC-RSTIN) VCC/VCCQ stable to RSTIN# REC T (RSTIN) RSTIN# asserted pulse width W T (BUSY0) RSTIN (BUSY1) RSTIN (VCC-BUSY0) VCC/VCCQ stable to BUSY# P Tsu (RSTIN-AVD) RSTIN# Tsu (BUSY-CE) BUSY# Trise (RSTIN) ...

Page 79

... FBGA 128MB (1Gb) dimensions: 9.0 ±0 12.0 ±0 1.1 ±0.1 mm Ball pitch: 0.8 mm 9.0 0. INDEX 4X 0.15 Top Symbol Ordering info b MD2534-d2G-X-P b SDED7-256M-N9 b SDED5-512M-N9 Figure 35: Mechanical Dimensions 9x12 FBGA Package 79 mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet 1.1±0.1 0.26±0.04 b Side Dimensions in mm Min Nom Max 0.41 0.46 0.51 ...

Page 80

Rev. 1.3 10.4.2 mDOC H3 4Gb (512MB)/8Gb (1GB) FBGA dimensions: 10.0 ±0 14.0 ±0 1.1 ±0.1 mm Ball pitch: 0.8 mm 10±0.1 INDEX Top Figure 36: Mechanical Dimensions 10x14 FBGA Package 80 mDOC H3 EFD Featuring ...

Page 81

... FBGA dimensions: 12.0 ±0 18.0 ±0 1.3 ±0.1 mm Ball pitch: 0.8 mm Symbol Ordering Info h SDED7-001G-NT h SDED7-002G-NT h SDED5-002G-NC h SDED5-004G-NC h SDED5-008G-NC Figure 37: Mechanical Dimensions 12x18 FBGA Package 81 Product Specifications mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet Max Height(mm) 1.4 1.4 1.2 1.2 1.4 92-DS-1205-10 ...

Page 82

... SDED7-256M-N9T SDED7-256M-N9Y SDED7-512M-NAT SDED7-512M-NAY SDED5-512M-N9T SDED5-512M-N9Y SDED5-001G-NAT SDED5-001G-NAY SDED5-002G-NCT SDED5-002G-NCY SDED5-004G-NCT SDED5-004G-NCY SDED5-008G-NCT SDED5-008G-NCY Notes: 1. SDE Product Codes: T suffix specifies shipment in Tape & Reel; Y suffix specifies shipment in trays Product Codes:: Y suffix specifies shipment in trays; if not specified, shipment is in Tape & Reel 82 ...

Page 83

Rev. 1.3 12. M ARKINGS 12.1 mDOC H3 1Gb (128MB) Markings for MD2533-d1G XXX and MD2533-d26G XXX products: First row: Logo Second row: Product name Third row: Ordering information Fourth row: Production information: yyww - Year and week xx - ...

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Rev. 1.3 12.2 mDOC H3 2Gb (256MB)/ 4Gb (512MB)/ 8Gb (1GB)/ 16Gb (2GB)/ 32Gb (4GB) / 64Gb (8GB) All products with ordering info of SDE-ZZ-XXXY-BBB will have following marking: First row: Logo Second row: VYWWXXXXN V-Internal use Y-year WW-work week ...

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... SanDisk IL shall not be liable for any loss, injury or damage caused by use of the Products in any of the following applications: Special applications such as military related equipment, nuclear reactor control, and aerospace ...

Page 86

... Per SanDisk IL’s Terms and Conditions of Sale, the user of SanDisk IL’s products in life support applications assumes all risk of such use and indemnifies SanDisk IL against all damages. See “Disclaimer of Liability". Accordingly, in any use of the Product in life support systems or other applications where failure could cause injury or loss of life, the Product should only be incorporated in systems designed with appropriate and sufficient redundancy or backup features ...

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