LTC4257IS8-1 Linear Technology, LTC4257IS8-1 Datasheet - Page 16

• Manufacturer Part Number: LTC4257IS8-1
• Description: IC CONTROLLER POE INTERFAC 8SOIC
• Manufacturer: Linear Technology
• Type: Power over Ethernet Switch (PoE)r

Specifications of LTC4257IS8-1

• Applications: IP Phones, Power over LAN, Network Routers and Switches
• Internal Switch(s): Yes
• Current Limit: 350mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC4257-1
that the transformer maintain the voltage between 38V and
57V to keep the LTC4257-1 in its normal operating range.
The third option has the advantage of automatically dis-
abling the 25k signature when the external voltage ex-
ceeds the PSE voltage.
Classification Resistor Selection (R
The IEEE specification allows classifying PDs into four
distinct classes with class 4 being reserved for future use
(Table 2). An external resistor connected from R
V
designer should determine which power category the PD
falls into and then select the appropriate value of R
from Table 2. If a unique load current is required, the value
of R
where I
during classification and is given in the electrical speci-
fications. The R
avoid degrading the overall accuracy of the classification
circuit. Resistor power dissipation will be 50mW maxi-
16
IN
R
(Figure 4) sets the value of the load current. The
CLASS
CLASS
IN_CLASS
can be calculated as:
= 1.237V/(I
CLASS
is the LTC4257-1 IC supply current
U
DESIRED
resistor must be 1% or better to
PSE
PSE
TO
U
TO
–48V
–48V
– I
IN_CLASS
4
4
W
V
V
LTC4257-1
IN
LTC4257-1
IN
CLASS
PWRGD
PWRGD
Figure 10. Power Good Interface Examples
V
V
GND
GND
)
OUT
OUT
ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULLUP
)
ACTIVE-LOW ENABLE, 5.1V SWING
8
6
8
6
5
5
*C15 OPTIONAL TO FILTER PWRGD.
*C15 AND C17 OPTIONAL TO FILTER PWRGD.
SEE APPLICATIONS INFORMATION
+
SEE APPLICATIONS INFORMATION
+
U
CLASS
C1
5µF
100V
C1
5µF
100V
CLASS
to
R9
100k
R9
100k
R18
10k
R18
10k
mum and is transient so heating is typically not a con-
cern. In order to maintain loop stability, the layout should
minimize capacitance at the R
tion circuit can be disabled by floating the R
R
force the LTC4257-1 classification circuit to attempt to
source very large currents. In this case, the LTC4257-1
will quickly go into thermal shutdown.
Power Good Interface
The PWRGD signal is controlled by a high voltage, open-
drain transistor. Examples of active-high and active-low
interface circuits for controlling the PD load are shown in
Figure 10.
In some applications it is desirable to ignore intermittent
power bad conditions. This can be accomplished by
including capacitor C15 in Figure 10 to form a lowpass
filter. With the components shown, power bad conditions
less than about 200µs will be ignored. Conversely, in other
applications it may be desirable to delay assertion of
PWRGD to the PD load. The PWRGD signal can be delayed
with the addition of capacitor C17 in Figure 10.
D6
MMBD4148
D6
5.1V
MMBZ5231B
CLASS
pin should not be shorted to V
FMMT2222
C15*
0.047µF
10V
C15*
0.047µF
10V
INTERNAL
PULLUP
Q1
SHDN
LOAD
PD
C17*
RUN
LOAD
PD
42571 F10
CLASS
node. The classifica-
IN
CLASS
as this would
pin. The
42571fb