ISL9502CRZ Intersil, ISL9502CRZ Datasheet - Page 17

• Manufacturer Part Number: ISL9502CRZ
• Description: IC CTRLR PWM 2PHASE GPU 48-QFN
• Manufacturer: Intersil

Specifications of ISL9502CRZ

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 500kHz
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -10°C ~ 100°C
• Package / Case: 48-VQFN
• Frequency-max: 500kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -

Static Mode of Operation - Remote Differential
Sensing
Remote differential sensing is the ability of the controller to
regulate the core output voltage at a remotely sensed point.
This allows the voltage regulator to compensate for various
resistive drops in the power path and ensure that the voltage
seen at the GPU is the correct level independent of load
current.
The VSEN and RTN pins of the ISL9502 are connected to
the desired Kelvin sense points at the processor. This allows
the voltage regulator to tightly control the processor voltage
at the point of load, independent of layout inconsistencies
and voltage drops. This Kelvin sense technique provides for
extremely tight load line regulation. Some GPUs may
provide two dedicated pins that report the core voltage on
chip. These can be used to further increase accuracy by
eliminating impedances found in the GPU socket.
These traces should be laid out as noise sensitive traces.
For optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads at the
processor must be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. To achieve
optimum performance, place common mode and differential
mode RC filters to analog ground on VSEN and RTN as
shown in Figure 23. The filter resistors should be 10Ω so that
they do not interact with the 50kΩ input resistance of the
differential amplifier. The filter resistor may be inserted
between +VOUT_SENSE and VSEN pin. Another option is
to place to the filter resistor between +VOUT_SENSE and
VSEN pin and between -VOUT_SENSE and RTN pin. The
ISEN1
OC
VDIFF
INTERNAL TO
ISL9502
ISEN1
0.018µF
FIGURE 23. SIMPLIFIED SCHEMATIC FOR DROOP AND DIE SENSING WITH INDUCTOR DCR CURRENT SENSING
-
+
+
+
ISEN2
10µA
R
OPN2
RTN
1
1
+
+
-
-
ISEN2
0.018µF
82nF
DROOP
VSEN
17
+
-
DROOP
OCSET
VSUM
10
DFB
R
+VOUT_SENSE
-VOUT_SENSE
opn1
VO'
R
drp2
R
OCSET
R
TO C
drp1
Cn
TO DESIRED POINT
REGULATION
BULK
R
VO'
R
SERIES
NTC
ISL9502
VSUM
R
PAR
VO'
need for these RC filters depends on the actual board layout
and noise environment.
If on chip Kelvin sensing is used, it is recommended to
include two resistors to assure a closed-loop output
connection if the GPU is not present. Figure 23 illustrates the
use of R
connection to output capacitance. These resistors typically
range from 20 to 100Ω.
Setting the Switching Frequency - FSET
The R
architecture. The switching frequency can increase during
the application of a load to improve transient performance.
It also varies slightly due changes in input and output voltage
and output current, but this variation is normally less than
10% in continuous conduction mode.
Refer to Figure 19, the resistor connected between the VW
and COMP pins of the ISL9502 adjusts the switching
window, and therefore adjusts the switching frequency. The
R
converter operating in CCM can be determined using the
following relationship, where R
switching period is in µs. Place a 47pF capacitor in parallel
with the frequency set resistor for better noise immunity. In
discontinuous conduction mode (DCM), the ISL9502 runs in
period stretching mode. The switching frequency is
dependent on the load current level.
R
FSET
FSET
VSUM
VSUM
3
(
resistor that sets up the switching frequency of the
kΩ
modulator scheme is not a fixed frequency PWM
OPN1
I
I
PHASE1
PHASE2
)
≅
RS
RS
(
period µs
and R
OPN2
(
ISEN2
ISEN1
R
) 0.5
L
L2
–
R
2
L1
to make a local feedback
) 1.56
L 1
FSET
•
VO'
+
Vdcr
C
C L1
L2
is in kΩ and the
VO'
+
2
DCR
Vdcr
DCR
-
RO1
1
-
R
O2
ESR
July 17, 2006
C
V
BULK
OUT
(EQ. 4)
FN9275.1