ISL9502CRZ Intersil, ISL9502CRZ Datasheet - Page 21

• Manufacturer Part Number: ISL9502CRZ
• Description: IC CTRLR PWM 2PHASE GPU 48-QFN
• Manufacturer: Intersil

Specifications of ISL9502CRZ

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 500kHz
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -10°C ~ 100°C
• Package / Case: 48-VQFN
• Frequency-max: 500kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -

output voltage will deviate from the initial voltage reading. A
good compensation can limit the drift to 2mV. If the output
voltage is decreasing with temperature increase, that ratio
between the NTC thermistor value and the rest of the
resistor divider network has to be increased. The user
should follow the evaluation board value and layout of NTC
as much as possible to minimize engineering time.
The 1.8mV/A load line from the above example should be
adjusted by R
small current steps like 10A, as the droop gain might vary
between each 10A steps. Basically, if the max current is 40A,
the required droop voltage is 72mV. The user should have
40A load current on and look for 72mV droop. If the drop
voltage is less than 72mV, for example, 68mV. The new
value will be calculated by:
For the best accuracy, the effective resistance on the DFB and
VSUM pins should be identical so that the bias current of the
droop amplifier does not cause an offset voltage. In the
example above, the resistance on the DFB pin is R
parallel with Rdrop2, that is, 1K in parallel with 4.90K or 830Ω.
The resistance on the VSUM pin is Rn in parallel with RS
or 4.90K in parallel with 1.825K or 1392Ω. The mismatch in
the effective resistances is 1392 - 830 = 562Ω. Do not let the
mismatch get larger than 600Ω. To reduce the mismatch,
multiply both R
appropriate factor in the example is 1392/830 = 1.677.
Dynamic Mode of Operation - Dynamic Droop
Using DCR Sensing
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage could
sag excessively upon load application and potentially create a
system failure. The output voltage could also take a long period
of time to settle to its final value. This could be problematic if a
load dump were to occur during this time. This situation would
cause the output voltage to rise above the no load setpoint of
the converter and could potentially damage the GPU.
The L/DCR time constant of the inductor must be matched to
the Rn*Cn time constant as shown in the following equation:
Solving for Cn we now have the following equation:
Note, RO was neglected. As long as the inductor time
constant matches the Cn, Rn and Rs time constants as
given above, the transient performance will be optimum. As
in the static droop case, this process may require a slight
adjustment to correct for layout inconsistencies. For the
Rdrp2_new
-------------
DCR
C
n
L
=
=
---------------------------------- -
----------------------------------
R
R
n
n
---------------------------------- C
R
R
+
•
-------------
DCR
n
n
RS
RS
+
•
L
=
RS
RS
EQV
EQV
drp2
72mV
--------------- - Rdrp1
68mV
drp1
EQV
EQV
based on maximum current, not based on
and R
(
•
n
drp2
+
21
Rdrp2
by the appropriate factor. The
) Rdrp1
–
drp1
(EQ. 23)
(EQ. 24)
in
EQV
ISL9502
example of L = 0.36µH with 0.8mΩ DCR, Cn is calculated
below.
The value of this capacitor is selected to be 330nF. As the
inductors tend to have 20% to 30% tolerances, this cap
generally will be tuned on the board by examining the
transient voltage. If the output voltage transient has an initial
dip, lower than the voltage required by the load line, and
slowly increases back to the steady state, the cap is too
small and vice versa. It is better to have the cap value a little
bigger to cover the tolerance of the inductor to prevent the
output voltage from going lower than the spec. This cap
needs to be a high grade cap like X7R with low tolerance.
There is another consideration in order to achieve better
time constant match mentioned above. The NPO/COG
(class-I) capacitors have only 5% tolerance and a very good
thermal characteristics. But those caps are only available in
small capacitance values. In order to use such capacitors,
the resistors and thermistors surrounding the droop voltage
sensing and droop amplifier has to be resized up to 10X to
reduce the capacitance by 10X. But attention has to be paid
in balancing the impedance of droop amplifier in this case.
Dynamic Mode of Operation - Compensation
Parameters
Considering the voltage regulator as a black box with a
voltage source controlled by VSEL and a series impedance,
in order to achieve the desired load line, the series
impedance needs to match the load line impedance. The
compensation design has to target the output impedance of
the converter to be this value. There is a mathematical
calculation file available to the user. The power stage
parameters such as L and Cs are needed as the input to
calculate the compensation component values. Attention
has to be paid to the input resistor to the FB pin. Too high of
a resistor will cause an error to the output voltage regulation
because of bias current flowing in the FB pin. It is better to
keep this resistor below 3K when using this file.
Static Mode of Operation - Current Balance Using
DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL9502 through the
matching of the voltages present on the ISEN pins. The
ISL9502 adjusts the duty cycles of each phase to maintain
equal potentials on the ISEN pins. RL and CL around each
inductor, or around each discrete current resistor, are used
to create a rather large time constant such that the ISEN
voltages have minimal ripple voltage and represent the DC
current flowing through each channel's inductor. For
optimum performance, RL is chosen to be 10kΩ and CL is
selected to be 0.22µF. When discrete resistor sensing is
used, a capacitor most likely needs to be placed in parallel
with RL to properly compensate the current balance circuit.
C
n
=
------------------------------------------------------------------
parallel 5.87K, 1.825K
(
0.36µH
------------------- -
0.0008
)
≈
330nF
July 17, 2006
(EQ. 25)
FN9275.1