ISL6308ACRZ-T Intersil, ISL6308ACRZ-T Datasheet - Page 12

• Manufacturer Part Number: ISL6308ACRZ-T
• Description: IC CTRLR PWM BUCK 3PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6308ACRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The ISL6308A senses the channel load current by sampling
the voltage across the lower MOSFET r
Figure 5. A ground-referenced operational amplifier, internal
to the ISL6308A, is connected to the PHASE node through a
resistor, R
the voltage drop across the r
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, I
sampled and held as described in “Current Sampling” on
page 11. From Figure 5, the following equation for I
derived where I
Output Voltage Setting
The ISL6308A uses a digital to analog converter (DAC) to
generate a reference voltage based on the logic signals at
the REF1, REF0 pins. The DAC decodes the 2-bit logic
signals into one of the discrete voltages shown in Table 1.
Each REF0 and REF1 pins are pulled up to an internal 1.2V
voltage by weak current sources (40µA current, decreasing
to 0 as the voltage at the REF0, REF1 pins varies from 0 to
the internal 1.2V pull-up voltage). External pull-up resistors
or active-high output stages can augment the pull-up current
sources, up to a voltage of 5V. The DAC pin must be
connected to REF pin through a 1kΩ to 5kΩ resistor and a
filter capacitor (0.022µF) is connected between REF and
GND.
The ISL6308A accommodates the use of external voltage
reference connected to REF pin if a different output voltage
is required. The DAC voltage must be set at least as high as
the external reference. The error amp internal noninverting
input is the lower of REF or (DAC +300mV).
resistor divider (R
to VSEN pin to set the output voltage level as shown in
Figure 6. This method is good for generating voltages up to
2.3V (with the REF voltage set to 1.5V).
For this case, the output voltage can be obtained as follows:
It is recommended to choose resistor values of less than
500Ω for R
voltage DC accuracy.
OUT
I
A third method for setting the output voltage is to use a
n
=
=
I
L
V
⋅
REF
r
----------------------
DS ON
R
ISEN
S1
ISEN
(
⋅
(
--------------------------------- -
and R
R
. The voltage across R
L
)
S1
is the channel current.
P1
R
+
P1
, R
P1
R
P1
S1
resistors in order to get better output
)
) from the output terminal (V
+ −
V
DS(ON)
12
OFS
–
V
DROOP
of the lower MOSFET
ISEN
L
. The ISEN current is
DS(ON)
is equivalent to
, as shown in
n
(EQ. 4)
is
(EQ. 3)
OUT
ISL6308A
)
Voltage Regulation
In order to regulate the output voltage to a specified level, the
ISL6308A uses the integrating compensation network shown in
Figure 6. This compensation network insures that the steady
state error in the output voltage is limited only to the error in the
reference voltage (output of the DAC or the external voltage
reference) and offset errors in the OFS current source, remote
sense and error amplifiers. Intersil specifies the guaranteed
tolerance of the ISL6308A to include the combined tolerances
of each of these elements, except when an external reference
or voltage divider is used, then the tolerances of these
components has to be taken into account.
The ISL6308A incorporates an internal differential remote-
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the controller ground reference point,
resulting in a more accurate means of sensing output voltage.
Connect the microprocessor sense pins to the non-inverting
input, VSEN, and inverting input, RGND, of the remote-sense
amplifier. The droop voltage, VDROOP, also feeds into the
remote-sense amplifier. The remote-sense output, VDIFF, is
therefore equal to the sum of the output voltage, VOUT, and
the droop voltage. VDIFF is connected to the inverting input of
the error amplifier through an external resistor.
The output of the error amplifier, V
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Internal MOSFET drivers and
regulate the converter output so that the voltage at FB is equal
to the voltage at REF. This will regulate the output voltage to
be equal to Equation 5. The internal and external circuitry that
controls voltage regulation is illustrated in Figure 6.
V
OUT
TABLE 1. ISL6308A DAC VOLTAGE SELECTION TABLE
=
REF1
V
0
0
1
1
REF
±
V
OFST
–
V
DROOP
REF0
0
1
0
1
COMP
, is compared to the
September 9, 2008
0.600V
0.900V
1.200V
1.500V
VDAC
FN6669.0
(EQ. 5)