ISL6308ACRZ-T Intersil, ISL6308ACRZ-T Datasheet - Page 17

• Manufacturer Part Number: ISL6308ACRZ-T
• Description: IC CTRLR PWM BUCK 3PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6308ACRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The ISL6308A constantly monitors the difference between the
VSEN and RGND voltages to detect if an overvoltage event
occurs. Before, and during soft-start, while the DAC/REF is
ramping up, the overvoltage trip level is V
successful soft-start, the overvoltage trip level changes to
V
Specifications” Table on page 6). Should an OVP event be
triggered for either case, the threshold hysteresis is 100mV
(typical) below its trip point, as sensed at the VSEN pins.
During an OVP event, the OVP pin is pulled high and PGOOD
is pulled low. In addition to the OVP pin behavior, the normal
control loop behavior commands all LGATE signals high as
soon as the output voltage strays higher than the set point,
essentially protecting against OVP events long before the
OVP pin is triggered. Thusly, the OVP output is a duplicate
method of protection, allowing the user to implement
secondary measures of protection for cases where normal
circuit behavior is insufficient, or an additional level of
protection is desired. The ISL6308 continues to protect the
output in the fashion described for as long as the overvoltage
condition is present and bias is applied to the circuit.
At the inception of an overvoltage event, all LGATE signals
are commanded high, and the PGOOD signal is driven low.
This causes the controller to turn on the lower MOSFETs
and pull the output voltage below a level that might cause
damage to the load. The LGATE outputs remain high until
VDIFF falls to within the overvoltage limits explained above.
The ISL6308A will continue to protect the load in this fashion
as long as the overvoltage condition recurs.
Once an overvoltage condition ends the ISL6308A continues
normal operation and PGOOD returns high.
For designs where the output voltage is scaled with a
resistor divider (as shown in Figure 6), the highest DAC
reference should normally be selected, in order to give the
most useful fixed OVP trip point during soft-start, as well as
after soft-start, where the OVP trip is referenced to the DAC.
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6308A is designed to protect the load from any
overvoltage events that may occur. This is accomplished by
means of an internal 10kΩ resistor tied from PHASE to
LGATE, which turns on the lower MOSFET to control the
output voltage until the overvoltage event ceases or the input
power supply cuts off. For complete protection, the low side
MOSFET should have a gate threshold well below the
maximum voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
OVP_rise
(typically REF+150mV; see “Electrical
17
OVP
; upon
ISL6308A
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6308A is designed to detect this
and shut down the controller. This event is detected by
monitoring the voltage on the IREF pin, which is a local
version of V
If VSEN or RGND become opened, VDIFF falls, causing the
duty cycle to increase and the output voltage on IREF to
increase. If the voltage on IREF exceeds “VDIFF+1V”, the
controller will shut down. Once the voltage on IREF falls
below “VDIFF+1V”, the ISL6308A will restart at the
beginning of soft-start.
Overcurrent Protection
The ISL6308A detects overcurrent events by comparing the
droop voltage, V
shown in Figure 13. The droop voltage, set by the external
current sensing circuitry, is proportional to the output current
as shown in Equation 8. A constant 100µA flows through
R
voltage exceeds the OCSET voltage, the overcurrent
protection circuitry activates. Since the droop voltage is
proportional to the output current, the overcurrent trip level,
I
as shown in Equation 13.
Once the output current exceeds the overcurrent trip level,
V
the converter to begin overcurrent protection procedures. At
the beginning of overcurrent shutdown, the controller turns off
both upper and lower MOSFETs. The system remains in this
state for a period of 4096 switching cycles. If the controller is
still enabled at the end of this wait period, it will attempt a soft-
start (as shown in Figure 14). If the fault remains, the trip-retry
cycles will continue indefinitely until either the controller is
disabled or the fault is cleared. Note that the energy delivered
during trip-retry cycling is much less than during full-load
operation, so there is no thermal hazard.
R
MAX
DROOP
OCSET
OCSET
FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE
0A
0V
, can be set by selecting the proper value for R
, creating the OCSET voltage. When the droop
=
will exceed V
I
--------------------------------------------------------- -
OUT
MAX
OUTPUT VOLTAGE
OUTPUT CURRENT
100μA R
DROOP
sensed at the outputs of the inductors.
⋅
R
COMP
OCSET
⋅
, to the OCSET voltage, V
S
⋅
DCR
, and a comparator will trigger
September 9, 2008
OCSET
OCSET
(EQ. 13)
FN6669.0
, as
,