ISL6308ACRZ-T Intersil, ISL6308ACRZ-T Datasheet - Page 23

• Manufacturer Part Number: ISL6308ACRZ-T
• Description: IC CTRLR PWM BUCK 3PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6308ACRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

margin (better than 45°). Phase margin is the difference
between the closed loop phase at F
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R
C
locating the poles and zeros of the compensation network:
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
1. Select a value for R
4. Calculate R
2. Calculate C
3. Calculate C
3
) in Figure 20 and 21. Use the following guidelines for
value for R
R
If setting the output voltage to be equal to the reference
set voltage as shown in Figure 21, the design procedure
can be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 6), in order
to compensate for the attenuation introduced by the
resistor divider, the obtained R
multiplied by a factor of (R
the calculations remain unchanged, as long as the
compensated R
at 0.1 to 0.75 of F
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
frequency (to maximize phase boost at F
C
C
such that F
times F
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
R
C
2
1
2
3
3
=
=
=
=
=
-------------------------------------------- -
d
---------------------------------------------- -
2π R
------------------------------------------------------- -
2π R
--------------------- -
F
----------- - 1
------------------------------------------------ -
2π R
F
V
MAX
SW
SW
LC
OSC
R
⋅
⋅
⋅
1
P2
). F
–
2
1
2
2
2
3
3
⋅
V
such that F
for desired converter bandwidth (F
⋅
⋅
⋅
⋅
such that F
such that F
1
1
0.5 F
C
R
is placed below F
0.7 F
IN
C
SW
1
1
1
2
⋅
⋅
⋅
LC
⋅
⋅
F
value is used.
F
F
represents the per-channel switching
LC
CE
0
LC
SW
1
(to adjust, change the 0.5 factor to
(1kΩ to 5kΩ, typically). Calculate
–
Z1
P1
1
Z2
23
is placed at a fraction of the F
P
is placed at F
is placed at F
+ R
0dB
SW
2
CE
1
S
value needs be
, R
)/R
/F
(typically, 0.5 to 1.0
and 180°. The
2
LC
P
, R
. The remainder of
, the lower the F
P2
LC
LC
CE
3
, C
).
lower in
. Calculate C
.
1
, C
0
2
).
(EQ. 30)
(EQ. 31)
(EQ. 32)
(EQ. 33)
, and
LC
Z1
ISL6308A
3
,
frequency response of the modulator (G
compensation (G
G
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 22 shows an asymptotic plot of the DC/DC
converter’s gain vs frequency. The actual Modulator Gain
has a high gain peak dependent on the quality factor (Q) of
the output filter, which is not shown. Using the above
guidelines should yield a compensation gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
against the capabilities of the error amplifier. The closed loop
gain, G
by adding the modulator gain, G
compensation gain, G
multiplying the modulator transfer function and the
compensation transfer function and then plotting the
resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin. The mathematical model
presented makes a number of approximations and is
generally not accurate at frequencies approaching or
exceeding half the switching frequency. When designing
compensation networks, select target crossover frequencies
in the range of 10% to 30% of the per-channel switching
frequency, F
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
F
F
F
F
MOD
Z1
Z2
P2
P1
G
G
CL
FB
=
=
=
=
f ( )
f ( )
f ( )
------------------------------ -
2π R
-------------------------------------------------
2π
------------------------------ -
2π R
-------------------------------------------- -
2π R
CL
=
=
=
, is constructed on the log-log graph of Figure 22
⋅
⋅
⋅
⋅
(
G
d
----------------------------- -
1
R
1
--------------------------------------------------- - ⋅
s f ( ) R
⋅
2
SW
3
2
MAX
------------------------------------------------------------------------------------------------------------------------ -
(
MOD
1
1
V
1
⋅
⋅
⋅
1
1
+
C
+
C
-------------------- -
C
OSC
C
⋅
+
.
1
R
3
s f ( ) R
1
1
FB
⋅
s f ( ) R
f ( ) G
3
1
+
V
⋅
) C
C
⋅
) and closed-loop response (G
IN
C
⋅
⋅
⋅
(
⋅
2
2
C
FB
⋅
3
2
1
1
FB
---------------------------------------------------------------------------------------------------------- -
1
3
⋅
+
+
+
⋅
(in dB). This is equivalent to
C
f ( )
C
C
s f ( )
s f ( )
1
3
2
)
)
⋅
⋅
⋅
⎛
⎜
⎝
(
(
MOD
1
where s f ( )
R
ESR
1
1
+
+
+
s f ( ) R
R
s f ( ) ESR C
(in dB), to the feedback
+
,
3
DCR
⋅
) C
MOD
⋅
⋅
2
⋅
3
=
) C
⎛
⎜
⎝
), feedback
⋅
-------------------- -
C
C
2π f j
⋅
1
1
September 9, 2008
+
+
⋅
⋅ ⋅
s
C
C
CL
2
2
2
f ( ) L C
⎞
⎟
⎠
(EQ. 38)
(EQ. 36)
(EQ. 37)
(EQ. 34)
(EQ. 35)
):
⎞
⎟
⎠
FN6669.0
⋅
P2
⋅