ISL6308ACRZ-T Intersil, ISL6308ACRZ-T Datasheet - Page 19

• Manufacturer Part Number: ISL6308ACRZ-T
• Description: IC CTRLR PWM BUCK 3PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6308ACRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t
approximate power loss is P
A third component involves the lower MOSFET
reverse-recovery charge, Q
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q
conducted through the upper MOSFET across V
power dissipated as a result is P
Finally, the resistive part of the upper MOSFET is given in
Equation 19 as P
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 16, 17, 18 and 19. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 6x6 QFN package is approximately 4W at
room temperature. See “Layout Considerations” on page 25
for thermal transfer improvement suggestions.
When designing the ISL6308A into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P
integrated driver’s internal circuitry and their corresponding
P
P
UP 4 ,
Qg_TOT
UP 3 ,
P
UP 2 ,
≈
=
r
≈
DS ON
V
, due to the gate charge of MOSFETs and the
V
IN
(
IN
⋅
Q
⋅
)
⎛
⎜
⎝
rr
⋅
I
----- -
N
M
d
UP,4
⋅
F
⋅
–
SW
I
-------- -
⎛
⎜
⎝
PP
2
I
----- -
.
N
M
⎞
⎟
⎠
⎞
⎟
⎠
2
⋅
⎛
⎜
⎝
+
t
----
2
2
rr
I
--------- -
UP,2
PP
12
⎞
⎟
⎠
. Since the inductor current has
19
2
⋅
2
. In Equation 17, the
F
UP,3
.
SW
.
rr
IN
, it is
. The
(EQ. 19)
(EQ. 17)
(EQ. 18)
ISL6308A
average driver current can be estimated with Equations 20
and 21, respectively.
In Equations 20 and 21, P
power loss and P
loss; the gate charge (Q
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I
quiescent current with no load at both drive outputs; N
and N
phase, respectively; N
phases. The I
controller without capacitive load and is typically 75mW at
300kHz.
P
P
P
I
DR
Qg_TOT
Qg_Q1
Qg_Q2
FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
PVCC
=
Q2
⎛
⎝
3
-- - Q
2
=
=
PHASE
•
are the number of upper and lower MOSFETs per
=
Q
3
-- - Q
2
R
R
P
G2
LO2
⋅
G1
BOOT
HI2
Qg_Q1
R
Q*
R
LO1
HI1
G1
⋅
•
VCC product is the quiescent power of the
PVCC F
N
Qg_Q2
⋅
Q1
PVCC F
+
LGATE
P
+
PHASE
Qg_Q2
⋅
Q
UGATE
G1
G2
is the total lower gate drive power
SW
⋅
Qg_Q1
and Q
•
SW
⋅
N
+
N
is the number of active
Q2
I
Q2
R
⋅
Q
N
G2
⎞
⎠
is the total upper gate drive
R
⋅
G2
G
Q1
⋅
VCC
G1
•
N
G
N
) is defined at the
PHASE
⋅
R
C
PHASE
Q
N
GI2
GD
R
C
PHASE
C
is the driver total
GI1
GD
GS
C
GS
•
S
F
S
SW
September 9, 2008
D
+
D
(EQ. 21)
Q2
(EQ. 20)
I
C
Q
FN6669.0
DS
Q1
Q1
C
DS