ISL6722AABZ Intersil, ISL6722AABZ Datasheet - Page 9

• Manufacturer Part Number: ISL6722AABZ
• Description: IC CTRLR PWM SGL ENDED 16-SOIC
• Manufacturer: Intersil

Specifications of ISL6722AABZ

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 100%
• Voltage - Supply: 9 V ~ 18 V
• Buck: Yes
• Boost: Yes
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
SLOPE - Means by which the ISENSE ramp slope may be
increased for improved noise immunity or improved control
loop stability for duty cycles greater than 50%. An internal
current source charges an external capacitor to GND during
each switching cycle. The resulting ramp is scaled and
added to the ISENSE signal.
SLEEP (ISL6722A) - A logic level control input that disables
the IC and activates the low power standby mode. SLEEP is
active high.
SYNC (ISL6723A) - A bidirectional synchronization signal
used to coordinate the switching frequency of multiple units.
Synchronization may be achieved by connecting the SYNC
signal of each unit together or by using an external master
clock signal. The oscillator timing capacitor, C
required, even if an external clock is used. The first unit to
assert this signal assumes control.
RTCT - This is the oscillator timing control pin. The
operational frequency and maximum duty cycle are set by
connecting a resistor, R
timing capacitor, C
produces a sawtooth waveform with a programmable
frequency range of 100kHz to 1.0MHz. The charge time, t
the discharge time, t
maximum duty cycle, Dmax, can be calculated from the
Equations 1, 2, 3 and 4:
t
t
Dmax
Figure 4 may be used as a guideline in selecting the
capacitor and resistor values required for a given frequency.
COMP - COMP is the output of the error amplifier and the
input of the PWM comparator. The control loop frequency
compensation network is connected between the COMP and
FB pins.
The ISL6722A, ISL6723A feature a built-in full cycle
soft-start. Soft-start is implemented as a clamp on the
maximum COMP voltage.
FB - Feedback voltage input connected to the inverting input
of the error amplifier. The non-inverting input of the error
amplifier is internally tied to a reference voltage.
f
C
D
sw
≈
≈
0.655 R
–
=
R T
-------------------- -
T
=
D
•
t
+
1
C
•
C T LN
T
•
C
T
f
•
sw
•
C
T
⎛
⎝
0.001 R T 3.6
------------------------------------------ -
0.001 R T 1.9
T
Hz
, from this pin to LGND. The oscillator
D
, the switching frequency, f
T
S
•
•
, between V
–
–
9
⎞
⎠
REF
S
and this pin and a
T
, is still
sw
ISL6722A, ISL6723A
, and the
(EQ. 1)
(EQ. 2)
(EQ. 3)
(EQ. 4)
C
,
OV - Overvoltage monitor input pin. This signal is compared
to an internal 2.5V reference to detect an overvoltage
condition.
UV - Undervoltage monitor input pin. This signal is
compared to an internal 1.45V reference to detect an
undervoltage condition.
ISENSE - This is the input to the current sense comparators.
The IC has two current sensing comparators, a PWM
comparator for peak current mode control, and an
overcurrent protection comparator. The overcurrent
comparator threshold is adjustable through the ISET pin.
Exceeding the overcurrent threshold will start a delayed
shutdown sequence. Once an overcurrent condition is
detected, the soft-start charge current source is disabled and
a discharge current source is enabled. The soft-start
capacitor begins discharging, and if it discharges to less than
4.375V (sustained overcurrent threshold), a shutdown
condition occurs and the GATE output is forced low. At this
point a reduced discharge current takes over until the
soft-start voltage reaches 0.27V (Reset Threshold). The
GATE output remains low until the reset threshold is
attained. At this point a soft-start cycle begins.
If the overcurrent condition ceases, and then an additional
50µs period elapses before the shutdown threshold is
reached, no shutdown occurs and the soft-start voltage is
allowed to recharge.
LGND - LGND is a small signal reference ground for all
analog functions on this device.
PGND - This pin provides a dedicated ground for the output
gate driver. The LGND and PGND pins should be connected
externally using a short printed circuit board trace close to
the IC. This is imperative to prevent large, high frequency
switching currents from flowing through the ground
metallization inside the IC. (Decouple V
low ESR 0.1µF or larger capacitor.)
GATE - This is the device output. It is a high current power
driver capable of driving the gate of a power MOSFET with
peak currents of 1.0A. This GATE output is actively held low
when V
The output high voltage is clamped to ~ 13.5V. Voltages
exceeding this clamp value should not be applied to the
GATE pin. The output stage provides very low impedance to
overshoot and undershoot.
V
gate drive. Separate V
analog circuitry from the high power gate drive noise.
(Decouple V
capacitor.)
V
quiescent current, I
frequency of operation. To optimize noise immunity, bypass
C
CC
- This pin is for separate collector supply to the output
- V
CC
CC
is below the UVLO threshold.
is the power connection for the device. Although
C
to PGND with a low ESR 0.1µF or larger
CC
, is low, it is dependent on the
C
and PGnd helps decouple the IC’s
C
to PGND with a
July 11, 2007
FN9237.1