ISL6722AABZ Intersil, ISL6722AABZ Datasheet
ISL6722AABZ
Specifications of ISL6722AABZ
Available stocks
Related parts for ISL6722AABZ
ISL6722AABZ Summary of contents
Page 1
... Boost Regulators LGND SS Ordering Information COMP PART FB NUMBER* (Note) ISL6722AABZ 6722AABZ -40 to +105 16 Ld SOIC ISL6723AABZ 6723AABZ -40 to +105 16 Ld SOIC ISL6722AAVZ 6722AAVZ ISL6722AARZ 22AZ 12 VCC *Add “-T” suffix to part number for tape and reel packaging. 11 VREF NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets ...
Page 2
Functional Block Diagram (ISL6722A START/STOP UV COMPARATOR + ENABLE - + - BG LGND RESTART SLEEP DELAY ISET 0.8 ISENSE VREF S + 53µA OVERCURRENT + 100mV COMPARATOR SLOPE 0 CLAMP + COMP ...
Page 3
Functional Block Diagram (ISL6723A) VCC START/STOP UV COMPARATOR + ENABLE - + - BG LGND RESTART DELAY ISET 0.8 ISENSE - + 5k VREF S + 53µA + OVERCURRENT 100mV SLOPE 0 CLAMP + - COMP ERROR AMPLIFIER ...
Page 4
Typical Application - 48V Input Dual Output Flyback, 3.3V @ 2.5A, 1.8V @ 1.0A P9 VIN+ R1 36V TO 75V C1 R2 VIN- SLEEP VR1 ISOLATION C18 R24 C2 CR2 C5 CR6 C3 TP1 ...
Page 5
... Thermal Information Thermal Resistance (Typical) 16 Lead QFN (Note Lead SOIC (Note Lead TSSOP (Note Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = V < 20V 11kΩ 330pF +25°C A ...
Page 6
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < V Typical values are at T PARAMETER Blanking Time Gain ERROR AMPLIFIER Open Loop Voltage Gain Gain-Bandwidth Product Reference Voltage ...
Page 7
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < V Typical values are at T PARAMETER SLOPE COMPENSATION Charge Current Slope Compensation Gain Discharge Voltage GATE OUTPUT Gate Output Limit Voltage ...
Page 8
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < V Typical values are at T PARAMETER SYNCHRONIZATION (ISL6723A) Input High Threshold Input Pulse Width Input Frequency Range Input Impedance VOH VOL ...
Page 9
Pin Descriptions SLOPE - Means by which the ISENSE ramp slope may be increased for improved noise immunity or improved control loop stability for duty cycles greater than 50%. An internal current source charges an external capacitor to GND during ...
Page 10
V to LGND with a ceramic capacitor as close to the V CC and LGND pins as possible. The total supply current (I plus I ) will be higher depending on the load applied to GATE. Total current ...
Page 11
The minimum amount of slope compensation required corresponds to 1/2 the inductor downslope. However, adding excessive slope compensation results in a control loop that behaves more as a voltage mode controller than as current mode controller. DOWNSLOPE Downslope CURRENT SENSE ...
Page 12
For flyback topologies, V can be solved for in terms of n output voltage, current transducer components, and primary inductance yielding: ⋅ ⋅ ⎛ ⎞ ⋅ V --------------------------------------- - ------- - ...
Page 13
Figure 6 depicts overcurrent behavior during soft-start. ISENSE’ represents the scaled values of ISENSE at the input to the overcurrent comparator. SS ISET ISENSE GA TE FIGURE 6. PULSE-BY-PULSE OC BEHAVIOR DURING SS Although an overcurrent condition exists, a shutdown ...
Page 14
Design Criteria The following design requirements were selected: Switching Frequency 200kHz 36V to 75V 3.3V @ 2.5A OUT( 1.8V @ 1.0A OUT( 12V @ 50mA OUT(Bias ...
Page 15
For simplicity, only the final design is further described. An EPCOS EFD 20/10/7 core using N87 material gapped value of 25 nH/N was chosen. It has more than the L required air gap volume to store ...
Page 16
The losses associated with MOSFET operation may be divided into three categories: conduction, switching, and gate drive. The conduction losses are due to the MOSFET’s ON resistance. 2 • Pcond = r Iprms where r ...
Page 17
For purposes of this discussion we will assume the following: 3.3V output: 100mV total output ripple and noise ESR: 60mV Capacitor ΔQ: 10mV ESL: 30mV 1.8V output: 50mV total output ripple and noise ESR: 30mV Capacitor ΔQ: 5mV ESL: 15mV ...
Page 18
There is limited flexibility to adjust the current loop behavior due to the need to provide overcurrent protection. Current limit and the current loop gain are determined by the current sense resistor and the ISET threshold. ISET was set at ...
Page 19
A Bode plot of the closed loop system at low line, max load appears below -10 -20 -30 -40 -50 0.01 0.1 1 FREQUENCY (kHz) FIGURE 12A. GAIN 200 150 100 ...
Page 20
Waveforms Typical waveforms can be found in Figures 13 through 15. These waveforms are taken from an ISL6721EVAL1 evaluation board, and therefore include synchronization waveforms that are not applicable to the ISL6722A, but are otherwise representative. Figure 13 shows the ...
Page 21
... Resistor, 2512, 1% Resistor, 0603, 1% Resistor, 0603, 1% OMIT Transformer, MIDCOM 31555 Opto-coupler, NEC PS2801-1 Shunt Reference, National LM431BIM3 PWM, Intersil ISL6722AABZ Zener, 15V, Zetex BZX84C15 [2] Dixon, Lloyd H., “Closing the Feedback Loop”, Unitrode Power Supply Design Seminar, SEM-700, 1990. DESCRIPTION July 11, 2007 FN9237.1 ...
Page 22
Package Outline Drawing L16.3x3B 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 4/07 3.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 2. 80 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 22 ISL6722A, ISL6723A ...
Page 23
Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX 0.25(0.010) E AREA E1 - 0.05(0.002) SEATING PLANE - -C- α 0.10(0.004) 0.10(0.004 NOTES: 1. These package ...
Page 24
... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...