ISL6244CR Intersil, ISL6244CR Datasheet - Page 14

• Manufacturer Part Number: ISL6244CR
• Description: IC CTRLR PWM 2-4-PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6244CR

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 4
• Frequency - Max: 4MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 4MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

In most cases, each channel uses the same R
sense current. A more complete expression for V
derived by combining equations 15 and 16.
Droop is an optional feature of the ISL6244. If active voltage
positioning is not required, simply leave the IOUT pin open.
REFERENCE OFFSET
Typical microprocessor tolerance windows are centered
around a nominal DAC set point. Implementing a load-line
would require offsetting the output voltage above this
nominal DAC set point, centering the load-line within the
static specification window. The ISL6244 features an internal
100µA current source which feeds out the OFS pin. Placing
a resistor from OFS and ground allows the user to set the
amount of positive offset desired directly to the reference
voltage. The voltage developed across the OFS resistor,
R
counters the DAC voltage at the error amplifier non-inverting
input. Select the resistor value based on the voltage offset
desired, V
DYNAMIC VID
Next generation microprocessors can change VID inputs at
any time while the regulator is in operation. The power
management solution is required to monitor the DAC inputs
and respond to VID voltage transitions or ‘on-the-fly’ VID
changes, in a controlled manner, supervising the safe output
voltage transition within the DAC range of the processor
without discontinuity or disruption.
The ISL6244 will register a VID change within 1 to 2 clock
cycles. If the VID change is stable for an additional 1 to 2
clock cycles, the controller will begin executing the output
voltage change. The controller begins incrementing the
reference voltage by making 25mV steps every two
switching cycles until it reaches the new VID code.
The total time required for a VID change, t
on the switching frequency (f
(∆VID), and the time before the next switching cycle begins.
Since the ISL6244 recognizes VID-code changes only at the
beginning of switching cycles, up to one full cycle may pass
before a VID change registers. This is followed by a one-
cycle wait before the output voltage begins to change. The
uncertainty in Equation 9 is due to the possibility that the VID
code change may occur between two and four full cycles
before being recognized.
V
R
---- -
f
2
S
OFS
DROOP
OFS


-------------- -
0.025
∆
VID
, is divided down internally by a factor of 5 and directly
=
5 V
---------------------- -
+
=
100µA
OFS
⋅
1


I
------------ -
OUT
OFS
<
N
, using Equation 19.
t
DV
r
---------------------- R
DS ON
R
≤
ISEN
(
---- -
f
2
S


)
-------------- -
0.025
∆
VID
FB
S
14
), the size of the change
+
2


DV
, is dependent
ISEN
DROOP
value to
(EQ. 9)
(EQ. 7)
(EQ. 8)
is
ISL6244
The time required for a converter running with f
to make a 1.2V to 1.4V reference-voltage change is between
72µs and 80µs as calculated using Equation 9. This example
is also illustrated in Figure 7.
Operation Initialization
Before converter operation is initialized, proper conditions
must exist on the enable and disable inputs. Once these
conditions are met, the controller begins a soft-start interval.
Once the output voltage is within the proper window of
operation, the PGOOD output changes state to update an
external system monitor.
Enable and Disable
The PWM outputs are held in a high-impedance state to
assure the drivers remain off while in shutdown mode. Three
separate input conditions must be met before the ISL6244 is
released from shutdown mode.
First, the bias voltage applied at VCC must reach the internal
power-on reset (POR) circuit rising threshold. Once this
threshold is met, proper operation of all aspects of the
ISL6244 is guaranteed. Hysteresis between the rising and
falling thresholds insures that once enabled, the ISL6244 will
not inadvertently turn off unless the bias voltage drops
substantially. See the Electrical Specifications for specifics
on POR rising and falling thresholds.
1.2V
1.2V
FIGURE 19. DYNAMIC-VID WAVEFORMS FOR 250kHz ISL6244
V
V
01110
REF
OUT
, 100mV/div
, 100mV/div
BASED MULTI-PHASE BUCK CONVERTER
00110
VID CHANGE OCCURS
ANYWHERE HERE
V
15µs/DIV
ID
, 5V/div
December 28, 2004
S
= 250kHz
FN9106.3