ISL6244CR Intersil, ISL6244CR Datasheet - Page 16

• Manufacturer Part Number: ISL6244CR
• Description: IC CTRLR PWM 2-4-PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6244CR

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 4
• Frequency - Max: 4MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 4MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

NOTE: Switching frequency 500kHz and R
Fault Monitoring and Protection
The ISL6244 actively monitors voltage and current feedback
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indication signal is provided for linking
to external system monitors. The schematic in Figure 23
outlines the interaction between the fault monitors and the
power good signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
which indicates that the converter is operating properly and
the output voltage is within a set window. The under-voltage
(UV) and over-voltage (OV) comparators create the output
voltage window. The controller also takes advantage of
current feedback to detect output over-current (OC)
conditions. PGOOD pulls low during shutdown and releases
high during soft-start once the output voltage reaches the
DAC level. Once high, PGOOD will only transition low when
the controller is disabled or a fault condition is detected. It
will return high under certain circumstances once a fault
clears.
Under-Voltage Protection
The voltage on V
is compared with the DAC reference voltage. By positively
offsetting the output voltage, an UV threshold is created
which moves relative to the VID code. During soft-start, the
slow rising output voltage eventually exceeds the UV
threshold. If a fault condition arises during operation and the
output voltage drops below the UV threshold, PGOOD will
immediately pull low, but converter operation will continue.
PGOOD will return high once the output voltage again
reaches regulation.
FIGURE 22. SOFT-START WAVEFORMS FOR ISL6244 BASED
MULTI-PHASE BUCK CONVERTER
t
DELAY
DIFF
is internally offset by 350mV before it
t
RAMP1
16
t
RAMP2
FB
VOUT, 500mV/DIV
EN, 5V/DIV
1ms/DIV
= 2.67kΩ.
ISL6244
If the ISL6244 is disabled during operation, the PGOOD
signal will not pull low until the output voltage decays below
the UV threshold.
Over-Voltage Protection
When the output of the differential amplifier (VDIFF) reaches
2.2V, PGOOD immediately goes low indicating a fault. Two
protective actions are taken by the ISL6244 to protect the
microprocessor load.
All PWM outputs are commanded low, directing the Intersil
drivers to turn on the lower MOSFETs. This shunts the
output to ground preventing any further increase in output
voltage. The PWM outputs remain low until VDIFF falls to the
programmed DAC level at which time they go into a high-
impedance state. The Intersil drivers respond by turning off
both upper and lower MOSFETs. If the over-voltage
condition recurs, the ISL6244 will again command the lower
MOSFETs to turn on. The ISL6244 will continue to protect
the load in this fashion as long as the over-voltage repeats.
Once an over-voltage condition is detected, normal PWM
operation ceases and PGOOD remains low until the
ISL6244 is reset. Cycling the voltage on EN below 1.23V or
the bias to VCC below the POR-falling threshold will reset
the controller.
Over-Current Protection
The ISL6244 monitors individual channel current to detect an
over-current condition. Each channel current is continually
compared with a constant 85µA reference current. Once any
of the currents exceeds the reference current, the comparator
triggers the converter to shutdown. The POR circuit places all
PWM signals in a high-impedance state which commands the
drivers to turn off both upper and lower MOSFETs. PGOOD
pulls low and the system remains in this state while the
controller counts 2048 phase clock cycles. This is followed by
a soft-start attempt (see Soft-Start).
VDIFF
FIGURE 23. POWER GOOD AND PROTECTION CIRCUITRY
REFERENCE
DAC
UV
2.2V
350mV
+
-
+
-
OV
CIRCUIT
POR
OC
December 28, 2004
+
-
FN9106.3
PGOOD
85µA
I
CHx