ISL6244CR Intersil, ISL6244CR Datasheet - Page 18

• Manufacturer Part Number: ISL6244CR
• Description: IC CTRLR PWM 2-4-PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6244CR

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 4
• Frequency - Max: 4MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 4MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

UPPER MOSFET POWER CALCULATION
In addition to r
MOSFET losses are due to currents conducted across the
input voltage (V
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverse-
recovery charge, Q
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 16,
the required time for this commutation is t
approximated associated power loss is P
The upper MOSFET begins to conduct and this transition
occurs over a time t
loss is P
A third component involves the lower MOSFET’s reverse-
recovery charge, Q
commutated to the upper MOSFET before the lower-
MOSFET’s body diode can draw all of Q
through the upper MOSFET across VIN. The power
dissipated as a result is P
Finally, the resistive part of the upper MOSFET’s is given in
Equation 19 as P
In this case, of course, r
upper MOSFET.
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 16, 17, 18 and 19. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process that involves
repetitively solving the loss equations for different MOSFETs
and different switching frequencies until converging upon the
best solution.
P
P
P
P
UP 1 ,
UP 2 ,
UP 3 ,
UP 4 ,
≈
≈
≈
=
V
r
V
UP,2
DS ON
V
IN
IN
IN
(





I
----- -
Q
I
----- -
N
.
N
M
M
rr
DS(ON)
)
+
–
IN
f
S



I
-------- -
I
-------- -
UP,4
PP
PP
I
----- -
) during switching. Since a substantially
2
2
N
M
rr
rr
2



 t

 t


. In Equation 17, the approximate power
; and the upper MOSFET r
. Since the inductor current has fully
2






.
d
losses, a large portion of the upper-
----
----
2
2
2
1
+



DS(ON)



I
--------- -
f
f
UP,3
PP
12
S
S
2
18
and is approximately
is the on resistance of the
rr
UP,1
1
, it is conducted
and the
.
DS(ON)
(EQ. 16)
(EQ. 17)
(EQ. 18)
(EQ. 19)
ISL6244
Current Sensing
The ISEN pins are denoted ISEN1, ISEN2, ISEN3 and
ISEN4. The resistors connected between these pins and
their respective phase nodes determine the gains in the
load-line regulation loop and the channel-current balance
loop. Select the values for these resistors based on the room
temperature r
operating current, I
according to Equation 20 (see also Figure 15).
In certain circumstances, it may be necessary to adjust the
value of one or more of the ISEN resistors. This can arise
when the components of one or more channels are inhibited
from dissipating their heat so that the affected channels run
hotter than desired (see the section entitled Channel-Current
Balance). In these cases, chose new, smaller values of R
for the affected phases. Choose R
desired decrease in temperature rise in order to cause
proportionally less current to flow in the hotter phase.
In Equation 21, make sure that ∆T
rise above the ambient temperature, and ∆T
temperature rise above the ambient temperature. While a
single adjustment according to Equation 21 is usually
sufficient, it may occasionally be necessary to adjust R
two or more times to achieve perfect thermal balance
between all channels.
Load-Line Regulation Resistor
The load-line regulation resistor is labeled R
17. Its value depends on the desired full-load droop voltage
(V
each ISEN resistor, the load-line regulation resistor is as
shown in Equation 22.
If one or more of the ISEN resistors was adjusted for thermal
balance, as in Equation 21, the load-line regulation resistor
should be selected according to Equation 23. Where I
the full-load operating current and R
resistor connected to the n
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
R
R
R
R
FB
ISEN
ISEN 2 ,
FB
DROOP
=
=
=
--------------------------------
I
V
------------------------ -
50 10
FL
V
DROOP
=
---------------------- -
50 10
r
DROOP
DS ON
×
in Figure 17). If Equation 20 is used to select
r
R
DS ON
×
ISEN
(
DS(ON)
–
(
6
–
6
)
∆T
----------
∆T
)
I
------- -
FL
FL
N
∑
n
2
1
; and the number of phases, N
of the lower MOSFETs; the full-load
R
ISEN n ( )
th
ISEN pin.
2
ISEN,2
is the desired temperature
ISEN(n)
in proportion to the
1
is the ISEN
is the measured
FB
December 28, 2004
in Figure
(EQ. 23)
(EQ. 20)
(EQ. 21)
(EQ. 22)
ISEN
FN9106.3
FL
ISEN
is