ISL6244CR Intersil, ISL6244CR Datasheet - Page 17

• Manufacturer Part Number: ISL6244CR
• Description: IC CTRLR PWM 2-4-PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6244CR

• Pwm Type: Voltage/Current Mode
• Number Of Outputs: 4
• Frequency - Max: 4MHz
• Duty Cycle: 75%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 4MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

During the soft-start interval, the over-current protection
circuitry remains active. As the output voltage ramps up, if
an over-current condition is detected, the ISL6244
immediately places all PWM signals in a high-impedance
state. The ISL6244 repeats the 2048-cycle wait period and
follows with another soft-start attempt, as shown in
Figure 24. This hiccup mode of operation repeats up to
seven times. On the eighth soft-start attempt, the part
latches off. Once latched off, the ISL6244 can only be reset
when the voltage on EN is brought below 1.23V or VCC is
brought below the POR falling threshold. Upon completion of
a successful soft-start attempt, operation will continue as
normal, PGOOD will return high, and the OC latch counter is
reset.
During VID-on-the-fly transitions, the OC comparator output
is blanked. The quality and mix of output capacitors used in
different applications leads to a wide output capacitance
range. Depending upon the magnitude and direction of the
VID change, the change in voltage across the output
capacitors could result in significant current flow. Summing
this instantaneous current with the load current already
present could drive the average current above the reference
current level and cause an OC trip during the transition. By
blanking the OC comparator during the VID-on-the-fly
transition, nuisance tripping is avoided.
Application Information
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
applications.
FIGURE 24. OVERCURRENT BEHAVIOR IN HICCUP MODE
0A
0V
5ms/DIV
17
OUTPUT CURRENT, 20A/DIV
OUTPUT VOLTAGE,
500mV/DIV
ISL6244
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board and the total board space available for power-supply
circuitry. Generally speaking, the most economical solutions
are those where each phase handles between 15 and 20A.
In cases where board space is the limiting constraint, current
can be pushed as high as 30A per phase, but these designs
require heat sinks and forced air to cool the MOSFETs.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching frequency;
the capability of the MOSFETs to dissipate heat; and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (r
continuous output current; I
current (see Equation 1); d is the duty cycle (V
L is the per-channel inductance.
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
frequency, f
the beginning and the end of the lower-MOSFET conduction
interval respectively.
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of P
P
P
L
D
=
=
r
V
DS ON
D ON
(
(
S
DS(ON)
)
)
; and the length of dead times, t
f
S



I
----- -
N
M





I
----- -
N
M
2
). In Equation 14, I
(
+
1 d
I
-------- -
–
PP
2
)
 t

M
+
, V
d1
PP
I
--------------------------------
L PP
,
D(ON)
+
2
is the peak-to-peak inductor



12
(
I
----- -
N
M
1 d
–
; the switching
–
I
-------- -
PP
M
)
2
is the maximum



t
d2
d1
OUT
December 28, 2004
and t
L
/V
and P
IN
d2
(EQ. 14)
(EQ. 15)
FN9106.3
); and
, at
D
.