MAX17582GTM+ Maxim Integrated Products, MAX17582GTM+ Datasheet - Page 35

• Manufacturer Part Number: MAX17582GTM+
• Description: IC PWM CTRLR STP-DN DL 48TQFN
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX17582GTM+

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 4.5 ~ 5.5 V
• Number Of Outputs: 1
• Voltage - Output: 0.01 ~ 1.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX17582 features a thermal-fault-protection cir-
cuit. When the junction temperature rises above
+160°C, a thermal sensor sets the fault latch and acti-
vates the soft-shutdown sequence. Once the controller
ramps down to zero, it forces DL1 and DL2 high and
pulls DH1 and DH2 low. Toggle SHDN or cycle the V
power supply below 0.5V to clear the fault latch and
reactivate the controller after the junction temperature
cools by 15°C.
Thermal shutdown can be disabled through the no-fault
test mode (see the No-Fault Test Mode section).
The latched fault-protection features can complicate the
process of debugging prototype breadboards since
there are (at most) a few milliseconds in which to deter-
mine what went wrong. Therefore, a no-fault test mode is
provided to disable the fault protection—undervoltage
protection and thermal shutdown. Additionally, the test
mode clears the fault latch if it has been set. The no-fault
test mode is entered by forcing 11V to 13V on SHDN.
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V
V
(DH_) source and sink 2.2A, and the low-side gate dri-
vers (DL_) source 2.7A and sink 8A. This ensures
robust gate drive for high-current applications. The DH_
floating high-side MOSFET drivers are powered by
internal boost switch charge pumps at BST_, while the
DL_ synchronous-rectifier drivers are powered directly
by the 5V bias supply (V
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
There must be a low-resistance, low-inductance path
from the DL_ and DH_ drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly; other-
wise, the sense circuitry in the MAX17582 interprets the
MOSFET gates as off while charge actually remains.
Use very short, wide traces (50 mils to 100 mils wide if
the MOSFET is 1in from the driver).
OUT
differential exists. The high-side gate drivers
______________________________________________________________________________________
DD
Dual-Phase, Quick-PWM Controller for
).
MOSFET Gate Drivers
Thermal-Fault Protection
IMVP-6.5 CPU Core Power Supplies
No-Fault Test Mode
IN
CC
-
The internal pulldown transistor that drives DL_ low is
robust, with a 0.25Ω (typ) on-resistance. This helps
prevent DL_ from being pulled up due to capacitive
coupling from the drain to the gate of the low-side
MOSFETs when the inductor node (LX_) quickly
switches from ground to V
input voltages and long inductive driver traces might
require that rising LX_ edges do not pull up the low-
side MOSFETs’ gate, causing shoot-through currents.
The capacitive coupling between LX_ and DL_ created
by the MOSFET’s gate-to-drain capacitance (C
gate-to-source capacitance (C
tional board parasitics should not exceed the following
minimum threshold:
Typically, adding a 4700pF capacitor between DL_ and
power ground (C
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive
turn-off delays.
Figure 9. Gate Drive Circuit
(R
(C
BST_
NL
)* OPTIONAL—THE CAPACITOR REDUCES LX_ TO DL_ CAPACITIVE
)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE
SWITCHING NODE RISE TIME.
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
V
GS TH
PGND
BST_
NL
DH_
DL_
LX_
V
(
DD
in Figure 9), close to the low-side
)
>
(R
C
V
BYP
C
(C
IN
BST_
BST_
NL
⎛
⎝ ⎜
)*
)*
IN
C
C
. Applications with high
RSS
ISS
ISS
⎞
⎠ ⎟
- C
RSS
N
N
H
L
), and addi-
INPUT (V
L
IN
)
RSS
35
),