MAX17582GTM+ Maxim Integrated Products, MAX17582GTM+ Datasheet - Page 41

• Manufacturer Part Number: MAX17582GTM+
• Description: IC PWM CTRLR STP-DN DL 48TQFN
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX17582GTM+

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 4.5 ~ 5.5 V
• Number Of Outputs: 1
• Voltage - Output: 0.01 ~ 1.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If the calculated V
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
able V
calculate V
response.
Dropout design example:
V
f
t
V
V
h = 1.5 and η
Calculating again with h = 1 gives the absolute limit of
dropout:
Therefore, V
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 5.0V.
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Refer to the MAX17582 evaluation kit specifi-
cation for a layout example and follow these guidelines
for good PCB layout:
•
•
•
SW
OFF(MIN)
FB
DROOP
DROP1
Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
Connect all analog grounds to a separate solid cop-
per plane, which connects to the GND pin of the
Quick-PWM controller. This includes the V
and GNDS bypass capacitors.
Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
= 300kHz
= 1.4V
V
V
SAG
IN MIN
IN MIN
= V
(
= 3mV/A x 30A = 90mV
(
= 400ns
. If operation near dropout is anticipated,
IN
DROP2
150
)
150
SAG
)
TOTAL
=
=
must be greater than 4.1V, even with very
Applications Information
2
mV
2
mV
×
×
______________________________________________________________________________________
to be sure of adequate transient
IN(MIN)
= 150mV (30A Load)
⎡
⎢
⎣
-
⎡
⎢
⎣
-
= 2:
1 2
150
1 2
150
-
-
1 4
1 4
mV
×
mV
×
Dual-Phase, Quick-PWM Controller for
.
.
( .
PCB Layout Guidelines
( .
V
0 4
is greater than the required
V
0 4
+
+
-
-
90
90
μs
90
90
μs
IMVP-6.5 CPU Core Power Supplies
mV
mV
mV
mV
×
×
1 5
1 0
.
.
+
=
+
=
150
4 96
150
×
4 07
×
.
.
3 3 00
3 3 00
mV
mV
V
V
kHz
kHz
)
)
⎤
⎥ +
⎦
⎤
⎥ +
⎦
CC
, FB,
•
•
•
•
1) Place the power components first, with ground ter-
2) Mount the controller IC adjacent to the low-side
3) Group the gate-drive components (BST_ diodes
4) Make the DC-DC controller ground connections as
copper PCBs (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mΩ
of excess trace resistance causes a measurable
efficiency penalty.
Keep the high-current, gate-driver traces (DL_,
DH_, LX_, and BST_) short and wide to minimize
trace resistance and inductance. This is essential
for high-power MOSFETs that require low-imped-
ance gate drivers to avoid shoot-through currents.
CSP_ and CSN_ connections for current limiting
and voltage positioning must be made using Kelvin-
sense connections to guarantee the current-sense
accuracy.
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
Route high-speed switching nodes away from sen-
sitive analog areas (CCI, FB, CSP_, CSN_, etc.).
minals adjacent (low-side MOSFET source, C
C
connections on the top layer with wide, copper-
filled areas.
MOSFET. The DL_ gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is 1in
from the controller IC).
and capacitors, V
near the controller IC.
shown in Figure 1. This diagram can be viewed as
having four separate ground planes: input/output
ground, where all the high-power components go;
the power ground plane, where the GND pin and
V
ground plane, where sensitive analog components
go, and the master’s GND pin and V
capacitor go; and the slave’s analog ground plane,
where the slave’s GND pin and V
tor go. The master’s GND plane must meet the GND
plane only at a single point directly beneath the IC.
DD
OUT
bypass capacitor go; the master’s analog
, and D1 anode). If possible, make all these
DD
bypass capacitor) together
Layout Procedure
CC
bypass capaci-
CC
bypass
IN
41
,