DPA426SN Power Integrations, DPA426SN Datasheet - Page 13

• Manufacturer Part Number: DPA426SN
• Description: IC CONV DC-DC DPA SWITCH SPAK
• Manufacturer: Power Integrations
• Series: DPA-Switch®r

Specifications of DPA426SN

• Applications: Converter, Power Over Ethernet and Telecom Applications
• Voltage - Input: 16 ~ 75 V
• Number Of Outputs: 1
• Voltage - Output: 220V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SPak (5 leads + Tab)
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

adjustments to the loop gain and to allow the capacitor to perform
its other functions in the system.
The zero introduced by R4 and the ESR of C6 should be at
approximately 25% of the output filter resonant frequency. This
placement allows maximum gain reduction while minimizing the
phase lag introduced by this network at the resonant frequency.
In the prototype example, C6 is 68 µF with an ESR of about
1.6 Ω. The impedance at the CONTROL pin of DPA-Switch
is typically 15 Ω. These values put the pole at approximately
130 Hz and the zero at approximately 900 Hz. High frequency
bypass capacitor C5 is small enough to have a negligible effect
on the loop gain.
Optocoupler Compensation
The current transfer ratio (CTR) of the optocoupler is a major
contributor to the magnitude of the loop gain near the crossover
frequency. Equally important is the resistor R6 in series with
the optocoupler LED. Selection for either of these elements
is not arbitrary, as the optocoupler provides power to the
DPA-Switch during normal operation.
The combination of optocoupler and series resistor must
deliver the maximum specified CONTROL pin current for the
DPA-Switch at minimum specified CTR. In most cases, an
optocoupler with a CTR between 100% and 200% will suffice.
The designer then selects R6 to provide the LED current required
at minimum CTR with a saturated TL431. The network of
R12 and C16 in parallel with R6 creates a zero that boosts
the gain and phase to compensate one of the poles from the
output filter. The position of the zero is generally determined
empirically to achieve the desired phase margin. It is typically
set at a frequency between one and three times the resonant
frequency of the output filter. Resistor R12 limits the boost in
gain at high frequencies.
TL431 Compensation
The purpose of the TL431 is to provide high loop gain at
low frequencies. Its contribution is not necessary at higher
frequencies where the optocoupler provides adequate gain.
Therefore, the feedback circuit has compensation around the
TL431 to maximize its contribution at very low frequencies
and to remove its influence at higher frequencies.
The connection of C14 and R9 between the cathode and the
reference terminal of the TL431 allows maximum loop gain at
DC for the best voltage regulation. In the prototype example,
capacitor C14 forms an integrator that reduces the contribution
of the TL431 by 20 dB per decade. Resistor R9 with R10 sets the
minimum gain from the TL431 and introduces a zero in the loop
gain. The zero in the prototype example is at about 16 Hz.
Another zero, local to the TL431, is formed by C14 and R9
at about 720 Hz. The location of this zero is not critical for
normal operation in continuous conduction mode, and does not
appear in the loop gain of this example. It becomes important at
very light loads where the converter operates in discontinuous
conduction mode. The loop gain characteristic for discontinuous
conduction mode is fundamentally different from this example
of continuous conduction mode. The most significant effect is
that the loop gain will generally have a much lower crossover
frequency that depends on the load. The crossover frequency
could easily fall into the region where the TL431 contributes
significantly to the loop gain.
Loop Gain of Prototype Circuit
Figure 10 shows the magnitude and phase of the loop gain of the
prototype circuit for an input voltage of 72 V at a load current
of 5 A. The highest input voltage is typically the worst case in
forward converters because that is the condition for highest gain,
yielding the highest bandwidth and lowest phase margin.
The upper curve in Figure 10 is the magnitude of the loop
gain in units of dB. The lower curve is the phase in units of
degrees, with the scale shifted by 180 degrees to give the phase
margin directly. The markers Z1 through Z4 and P1 through
P6 show respectively the frequencies of the significant zeroes
and poles.
The integrator formed by C14, R9 and R10 reduces the gain
from its DC value such that the TL431 makes essentially no
contribution to the gain at frequencies higher than Z1. The
asymptotes of the DC value and the 20 dB per decade slope of
the integrator create the pole at P1.
Gain is reduced by the pole at P2 that is formed by capacitor
C6 with its ESR, resistor R4, and the internal impedance of
the CONTROL pin of the DPA-Switch. The phase receives
a boost from the zero formed by C6 and R4 with the ESR of
C6 at Z2. The resistor R4 augments the ESR of the capacitor.
Use a tantalum capacitor for C6 so that the total resistance
can be adjusted by R4. The ESR of an aluminum capacitor
will generally be too large to allow the desired shaping of the
frequency response. Capacitor C5 provides a low impedance
source for pulses of current into the CONTROL pin. Its effect
on the control loop is minor, appearing at P6, well beyond the
0 dB crossover frequency.
The zero at Z2 provides partial cancellation of the pair of poles P3,
P4 that originate from the output inductor and output capacitors
of the forward converter. The network of C16, R6 and R12 gives
additional cancellation with a zero at Z3. The ESR of the output
capacitors gives a final zero at Z4. The internal high frequency
filter of the DPA-Switch provides the pole at P5.
AN-31
7/04
C
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