E-L6919ETR STMicroelectronics, E-L6919ETR Datasheet - Page 16

• Manufacturer Part Number: E-L6919ETR
• Description: IC CTRLR 5BIT PROG 2PHASE 28SOIC
• Manufacturer: STMicroelectronics
• Type: Step-Down (Buck)r

Specifications of E-L6919ETR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 1.55 V
• Current - Output: 2A
• Frequency - Switching: 150kHz
• Voltage - Input: 5 ~ 12 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Power - Output: 2W
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 6.5 V
• Maximum Operating Temperature: 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4592-2

L6919E
Figure 10. Soft Start
INPUT CAPACITOR
The input capacitor is designed considering mainly the input RMS current that depends on the duty cycle as
reported in figure 11. Considering the dual-phase topology, the input RMS current is highly reduced comparing
with a single phase operation.
Figure 11. Input RMS Current vs. Duty Cycle (D) and Driving Relationships
It can be observed that the input rms value is one half of the single-phase equivalent input current in the worst
case condition that happens for D = 0.25 and D = 0.75.
The power dissipated by the input capacitance is then equal to:
Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the
high RMS value needed by the CPU power supply application and also to minimize components cost, the input
capacitance is realized by more than one physical capacitor. The equivalent RMS current is simply the sum of
the single capacitor's RMS current.
Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible
16/33
V
CC
=V
V
PGOOD
LGATEx
V
CCDR
OUT
0.50
0.25
Timing Diagram
0.25
2048 Clock Cycles
Duty Cycle (V
0.50
Turn ON threshold
Single Phase
Dual Phase
OUT
P
t
t
t
t
RM S
/V
IN
0.75
)
=
ESR
I
RM S
I
rms
(CH1=LGATEx; CH2=VCC; CH3=VOUT;
2





I
I
OUT
OUT
2
2
Acquisition:
2D
(2D
-
(1
1)
2
(2
D)
2
D)
if
if
D
D
0
0.5
5 .