E-L6919ETR STMicroelectronics, E-L6919ETR Datasheet - Page 20
![IC CTRLR 5BIT PROG 2PHASE 28SOIC](/photos/6/56/65690/stmicroelectronics-28-soic_sml.jpg)
E-L6919ETR
Manufacturer Part Number
E-L6919ETR
Description
IC CTRLR 5BIT PROG 2PHASE 28SOIC
Manufacturer
STMicroelectronics
Type
Step-Down (Buck)r
Datasheet
1.E-L6919ETR.pdf
(33 pages)
Specifications of E-L6919ETR
Internal Switch(s)
No
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
0.8 ~ 1.55 V
Current - Output
2A
Frequency - Switching
150kHz
Voltage - Input
5 ~ 12 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
Power - Output
2W
Mounting Style
SMD/SMT
Operating Supply Voltage
6.5 V
Maximum Operating Temperature
85 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-4592-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
L6919E
With further simplifications, it results:
Considering now that in the application of interest it can be assumed that Ro>>R
The ACM control loop gain is designed to obtain a high DC gain to minimize static error and cross the 0dB axes
with a constant -20dB/dec slope with the desired crossover frequency
the zero in correspondence with the L-C resonance a simple -20dB/dec shape of the gain is assured (See Figure
15). In fact, considering the usual value for the output filter, the LC resonance results to be at frequency lower
than the above reported zero.Compensation network can be simply designed placing
Figure 15. ACM Control Loop Gain Block Diagram (left) and Bode Diagram (right)
LAYOUT GUIDELINES
Since the device manages control functions and high-current drivers, layout is one of the most important things
20/33
R
transfer function has one zero and two poles. Both the poles are fixed once the output filter is designed and the
zero is fixed by ESR and the Droop resistance.
To obtain the desired shape an R
the cross-over frequency
DROOP
F
G
=1/R
L OO P
V
COMP
F
<<Ro, it results:
C
PWM
F
G
s
is then introduced together with an integrator. This integrator minimizes the static error while placing
L OO P
R
=
F
–
Z
=
F
4
-- -
5
d V
s
C
R
----------------------------------
F
------------------ -
IN
FB
=
V
V
O SC
R
G
IN
L/2
–
V
I
F
Cout
ESR
FB
4
-- -
5
LO O P
IN
T
V
as desired obtaining:
------------------ -
O SC
Z
-------------- -
V
REF
R
V
F
O SC
IN
FB
s
F
s
R
V
-C
5
-- -
4
OUT
FB
=
F
R o
------------------------------------- -
Rout
Z
-------------- -
–
R
series network is considered for the Z
F
T
4
-- -
5
FB
R o
+
s
------------------------------------------------------- -
2
------------------ -
R
V
+
V
DROOP
----------------------------------------------------------------------------------------------------------------------------------
s
OS C
R
------ -
IN
R
2
2
K
L
DROOP
=
Co L
K
----------------------------------- -
Z
4
-- -
5
L
P
----------------------------------------------------------------------------------------------------------------------------------
s
-- -
2
2
---------------
1
s
Z
+
+
V
V
dB
+
F
I N
o sc
C o
ESR
s
+
s Co
s
Z
L
1
---------------
2 Ro
----------
R
L
-- -
2
1
+
FB
s
L
+
s Co
s
dB
R
+
LC
Rs
------- -
Rg
DROOP
---------------
2 R o
C o ESR
T
. Neglecting the effect of Z
G
+
L
LOOP
R
Z
-------------- -
Z
R
DROOP
P
F
FB
+
(s) implementation. A zero at
+
C
s
Co ESR
ESR
F
+
=
C o
//Ro
------------------- -
Z
C o
=
R
R
------ -
L
+
2
F
; ESR<<Ro and
+
L
LC
Z
ESR
T
F
L
-- -
2
Co
(s)
+
and imposing
1
R
------ -
2
F
L
(s), the
+
1