IDT89HPES8NT2ZBBC8 IDT, Integrated Device Technology Inc, IDT89HPES8NT2ZBBC8 Datasheet

IDT89HPES8NT2ZBBC8

Manufacturer Part Number

IDT89HPES8NT2ZBBC8

Description

IC PCI SW 8LANE 2PORT 324-CABGA

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.IDT89HPES8NT2ZBBC8.pdf (28 pages)

Specifications of IDT89HPES8NT2ZBBC8

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

89HPES8NT2ZBBC8

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

IDT89HPES8NT2ZBBC8

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Current page: 1 of 28
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Device Overview

Express® switching solutions offering the next-generation I/O intercon-

nect standard. The PES8NT2 is a 8-lane, 2-port peripheral chip that

provides high-performance switching and non-transparent bridging

(NTB) functions between a PCIe® upstream port and an NTB down-

stream port. The PES8NT2 is a part of the IDT PCIe System Intercon-

nect Products and is intended to be used with IDT PCIe System

Interconnect Switches. Together, the chipset targets multi-host and intel-

ligent I/O applications such as communications, storage, and blade

servers where inter-domain communication is required.

Features

Block Diagram

The 89HPES8NT2 is a member of the IDT PRECISE™ family of PCI

◆

– Eight PCI Express lanes (2.5Gbps), two switch ports

– Delivers 32 Gbps (4 GBps) of aggregate switching capacity

– Low latency cut-through switch architecture

– Support for Max Payload size up to 2048 bytes

– Supports one virtual channel and eight traffic classes

– PCI Express Base specification Revision 1.0a compliant

– Supports automatic per port link width negotiation (x8, x4, x2,

– Static lane reversal on all ports

– Automatic polarity inversion on all lanes

High Performance PCI Express Switch

Flexible Architecture with Numerous Configuration Options

or x1)

SerDes

Logical

Frame Buffer

Layer

Phy

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

Multiplexer / Demultiplexer

Transaction Layer

Data Link Layer

SerDes

Logical

Layer

x4 Upstream Port and One x4 Downstream Port

Phy

8-Lane 2-Port Non-Transparent

PCI Express® Switch

...

SerDes

Logical

Layer

Route Table

Phy

Figure 1 Internal Block Diagram

8 PCI Express Lanes

2-Port Switch Core

1 of 28

◆

Arbitration

– Supports locked transactions, allowing use with legacy soft-

– Ability to load device configuration from serial EEPROM

– Ability to control device via SMBus

– Crosslink support on NTB port

– Four mapping windows supported

– Interprocessor communication

– Allows up to sixteen masters to communicate through the non-

– No limit on the number of supported outstanding transactions

– Completely symmetric non-transparent bridge operation

– Supports direct connection to a transparent or non-transparent

– Requires no external components

– Incorporates on-chip internal memory for packet buffering and

– Integrates eight 2.5 Gbps embedded full duplex SerDes, 8B/

Non-Transparent Port

Highly Integrated Solution

Port

ware

• Each may be configured as a 32-bit memory or I/O window

• May be paired to form a 64-bit memory window

• Thirty-two inbound and outbound doorbells

• Four inbound and outbound message registers

• Two shared scratchpad registers

transparent port

through the non-transparent bridge

allows similar/same configuration software to be run

port of another switch

queueing

10B encoder/decoder (no separate transceivers needed)

SerDes

Logical

Layer

Phy

Multiplexer / Demultiplexer

Transaction Layer

Data Link Layer

SerDes

Logical

Layer

Phy

...

Scheduler

Transparent

SerDes

Logical

Layer

Phy

Bridge

Non-

89HPES8NT2

January 5, 2009

Data Sheet

DSC 6925

Related parts for IDT89HPES8NT2ZBBC8

IDT89HPES8NT2ZBBC8 Summary of contents

Page 1

Device Overview The 89HPES8NT2 is a member of the IDT PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O intercon- nect standard. The PES8NT2 is a 8-lane, 2-port peripheral chip that provides high-performance switching and non-transparent bridging ...

Page 2

IDT 89HPES8NT2 Data Sheet ◆ Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC pass-through – Supports Hot-Swap ◆ ...

Page 3

IDT 89HPES8NT2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES8NT2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using ...

Page 4

IDT 89HPES8NT2 Data Sheet Signal MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] Type Name/Description I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information ...

Page 5

IDT 89HPES8NT2 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE PENTBRSTN PERSTN RSTHALT SWMODE[3:0] Signal JTAG_TCK JTAG_TDI Type Name/Description I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream ...

Page 6

IDT 89HPES8NT2 Data Sheet Signal JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE APE Type Name/Description O JTAG Data Output. This is the serial data shifted out from ...

Page 7

IDT 89HPES8NT2 Data Sheet Pin Characteristics Note: Some input pads of the PES8NT2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if ...

Page 8

IDT 89HPES8NT2 Data Sheet Function JTAG Pin Name Type Buffer JTAG_TCK I LVTTL JTAG_TDI I JTAG_TDO O JTAG_TMS I JTAG_TRST_N I Table 7 Pin Characteristics (Part I/O Internal Notes Type Resistor STI pull-up pull-up ...

Page 9

IDT 89HPES8NT2 Data Sheet Logic Diagram — PES8NT2 Reference Clocks PCI Express Switch SerDes Input Port A PCI Express Switch SerDes Input Port C Master SMBus Interface SSMBADDR[5,3:1] Slave SMBus Interface System Pins 2 PEREFCLKP 2 PEREFCLKN REFCLKM PEALREV PEARP[0] ...

Page 10

IDT 89HPES8NT2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. Parameter Refclk Input reference clock frequency range FREQ 2 Refclk Duty cycle of input ...

Page 11

IDT 89HPES8NT2 Data Sheet Parameter T Max time between jitter median & max deviation RX-EYE-MEDIUM TO MAX JITTER T Unexpected Idle Enter Detect Threshold Integration Time RX-IDLE-DET-DIFF- ENTER TIME T Lane to lane input skew RX-SKEW 1. Minimum, Typical, and ...

Page 12

IDT 89HPES8NT2 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol Parameter V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI ...

Page 13

IDT 89HPES8NT2 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 14. Maximum power is measured under the following conditions: ...

Page 14

IDT 89HPES8NT2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 12. Note: See Table 7, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Serial Link PCIe Transmit V ...

Page 15

IDT 89HPES8NT2 Data Sheet I/O Type Parameter Other I/Os LOW Drive I OL Output I OH High Drive I OL Output I OH Schmitt Trig ger Input V IH (STI) Input Capacitance C IN ...

Page 16

IDT 89HPES8NT2 Data Sheet Package Pinout — 324-BGA Signal Pinout for PES8NT2 The following table lists the pin numbers and signal names for the PES8NT2 device. Pin Function Alt Pin A1 V E10 E11 SS A3 PEARP03 ...

Page 17

IDT 89HPES8NT2 Data Sheet Pin Function Alt Pin B17 V CORE G8 DD B18 V CORE G10 G11 G12 CORE G13 G14 SS C6 ...

Page 18

IDT 89HPES8NT2 Data Sheet Pin Function Alt Pin D18 V CORE J10 E2 NC J11 E3 V CORE J12 J13 CORE J14 J15 J16 ...

Page 19

IDT 89HPES8NT2 Data Sheet Power Pins V Core V Core A10 F10 A12 F18 A14 G12 A15 B17 H10 B18 H12 C4 H18 C13 J6 C16 J9 ...

Page 20

IDT 89HPES8NT2 Data Sheet Ground Pins A17 A18 B10 B12 B14 B15 C11 D11 D13 D15 D16 G16 D17 H2 ...

Page 21

IDT 89HPES8NT2 Data Sheet Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE No Connect I/O Type Location ...

Page 22

IDT 89HPES8NT2 Data Sheet Signal Name PEALREV PEARN00 PEARN01 PEARN02 PEARN03 PEARP00 PEARP01 PEARP02 PEARP03 PEATN00 PEATN01 PEATN02 PEATN03 PEATP00 PEATP01 PEATP02 PEATP03 PECLREV PECRN00 PECRN01 PECRN02 PECRN03 PECRP00 PECRP01 PECRP02 PECRP03 PECTN00 PECTN01 PECTN02 PECTN03 PECTP00 PECTP01 PECTP02 PECTP03 ...

Page 23

IDT 89HPES8NT2 Data Sheet Signal Name PEREFCLKN0 PEREFCLKN1 PEREFCLKP0 PEREFCLKP1 PERSTN REFCLKM RSTHALT SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 V CORE APE ...

Page 24

IDT 89HPES8NT2 Data Sheet PES8NT2 Pinout — Top View Core (Power I/O (Power) ...

Page 25

IDT 89HPES8NT2 Data Sheet PES8NT2 Package Drawing — 324-Pin BC324/BCG324 January 5, 2009 ...

Page 26

IDT 89HPES8NT2 Data Sheet PES8NT2 Package Drawing — Page Two January 5, 2009 ...

Page 27

IDT 89HPES8NT2 Data Sheet Revision History April 15, 2008: Initial publication of data sheet. January 5, 2009: On the Ordering Information page, changed silicon revision from January 5, 2009 ...

Page 28

IDT 89HPES8NT2 Data Sheet Ordering Information A AAA NN Product Operating Device Family Family Voltage Valid Combinations 89HPES8NT2ZBBC 324-pin BC324 package, Commercial Temperature 89HPES8NT2ZBBCG 324-pin Green BC324 package, Commercial Temperature CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA ...

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