IDT89HPES8NT2ZBBC8 IDT, Integrated Device Technology Inc, IDT89HPES8NT2ZBBC8 Datasheet - Page 2

• Manufacturer Part Number: IDT89HPES8NT2ZBBC8
• Description: IC PCI SW 8LANE 2PORT 324-CABGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES8NT2ZBBC8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES8NT2ZBBC8

Product Description
the most efficient high-performance I/O connectivity solution for applica-
tions requiring high throughput, low latency, and simple board layout
with a minimum number of board layers. With support for non-trans-
parent bridging, the PES8NT2 is part of the IDT PCIe System Intercon-
nect Products that target multi-host and intelligent I/O applications
requiring inter-domain communication. The PES8NT2 provides 32 Gbps
(4 GBps) of aggregated, full-duplex switching capacity through 8 inte-
grated serial lanes, using proven and robust IDT technology. Each lane
provides 2.5 Gbps of bandwidth in both directions and is fully compliant
with PCI Express Base specification 1.0a.
ture. The PCI Express layer consists of SerDes, Physical, Data Link,
and Transaction layers in compliance with PCI Express Base specifica-
tion Revision 1.0a. The PES8NT2 can operate either as a store and
forward or cut-through switch depending on the packet size and is
designed to switch memory and I/O transactions. It supports eight Traffic
Classes (TCs) and one Virtual Channel (VC) with sophisticated resource
management.
IDT 89HPES8NT2 Data Sheet
Utilizing standard PCI Express interconnect, the PES8NT2 provides
The PES8NT2 is based on a flexible and efficient layered architec-
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– Internal end-to-end parity protection on all TLPs ensures data
– Supports ECRC pass-through
– Supports Hot-Swap
– Supports PCI Power Management Interface specification,
– Unused SerDes are disabled
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
– Slave interface provides full access to all software-visible
– Master interface provides connection for an optional serial
– Master and slave interfaces may be tied together so the switch
Reliability, Availability, and Serviceability (RAS) Features
Power Management
Testability and Debug Features
Two SMBus Interfaces
Eight General Purpose Input/Output pins
Packaged in 19x19mm 324 ball BGA with 1mm ball spacing
integrity even in systems that do not implement end-to-end
CRC (ECRC)
Revision 1.1 (PCI-PM)
registers by an external SMBus master
EEPROM used for initialization
can act as both master and slave
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Switch Configuration
lanes. Each of the two ports is statically allocated eight lanes with ports
labeled as A and C. Port A is the upstream port and port C is the non-
transparent downstream port.
PES8NT2 port is capable of independently negotiating to a x4, x2, or x1
width. Thus, the PES8NT2 may be used in virtually any two port switch
configuration (e.g., {x4, x4}, {x4, x2}, {x2, x2}, etc.). The PES8NT2
supports static lane reversal. For example, lane reversal for upstream
port A may be configured by asserting the PCI Express Port A Lane
Reverse (PEALREV) input signal or through serial EEPROM or SMBus
initialization. Lane reversal for port C may be enabled via a configura-
tion space register, serial EEPROM, or the SMBus.
The PES8NT2 is a two port switch that contains eight PCI Express
During link training, link width is automatically negotiated. Each
January 5, 2009