IDT72P51339L6BB8 IDT, Integrated Device Technology Inc, IDT72P51339L6BB8 Datasheet - Page 29
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IDT72P51339L6BB8
Manufacturer Part Number
IDT72P51339L6BB8
Description
IC FLOW CTRL 36BIT 256-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT72P51339L6BB8.pdf
(87 pages)
Specifications of IDT72P51339L6BB8
Configuration
Dual
Density
576Kb
Access Time (max)
3.7ns
Word Size
36b
Organization
2Kx36x8
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
BGA
Clock Freq (max)
166MHz
Supply Current
150mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72P51339L6BB8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72P51339L6BB8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
SWITCHING QUEUES ON THE WRITE PORT
trol devices can be configured up to a maximum of 8 queues. Data is written into
a queue using the Data Input (Din) bus, Write Clock (WCLK) and Write Enable
(WEN) signals. Selecting a queue occurs by placing the queue address on the
trol device supports changing (switching) queues every four (4) clock cycles.
To switch from the Present Queue (PQ) to another queue requires a queue
address to be placed on the Write Address Bus (WRADD) bus and a rising edge
of Write Clock (WCLK) and Write Address Enable (WADEN) is HIGH. There
are no restrictions as to the order to which queues are selected or switched into
or out of.
NOTES:
1. PQ = Present Queue
* Requires 4 clock cycles to switch queues.
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-
The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-
NQ = Next Queue
WADEN
WCLK
WEN
Din
WRADD
WADEN
WCLK
PQ
Queue
address
Figure 7. Write Port Switching Queues Signal Sequence
QS-1
Queue Switch Cycles *
PQ
Figure 8. Switching Queues Bus Efficiency
Queue Switch Cycle
QS0
PQ
QS1
PQ
29
Write Address bus (WRADD) during a rising edge of WCLK while Write Address
Enable (WADEN) is HIGH. For reference, the state of Write Enable (WEN) is
a “Don’t Care” during a queue selection. WEN has significance during the queue
mark operation. Selecting a queue requires 4 WCLK cycles. Refer to Figure
7, Write Port Switching Queues Signal Sequence.
the IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-control
device can continue to write into the Present Queue (PQ). The Present Queue
is defined as the current selected queue. Refer to Figure 8, Switching Queues
Bus Efficiency.
QS2
For maximum efficiency, during the 4 clock cycles required to switch queues
NQ
Queue
address
QS3
NQ
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
6716 drw13
AUGUST 4, 2005
6716 drw14