IDT72P51339L6BB8 IDT, Integrated Device Technology Inc, IDT72P51339L6BB8 Datasheet - Page 5
![IC FLOW CTRL 36BIT 256-BGA](/photos/31/30/313042/406-256-bga_sml.jpg)
IDT72P51339L6BB8
Manufacturer Part Number
IDT72P51339L6BB8
Description
IC FLOW CTRL 36BIT 256-BGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT72P51339L6BB8.pdf
(87 pages)
Specifications of IDT72P51339L6BB8
Configuration
Dual
Density
576Kb
Access Time (max)
3.7ns
Word Size
36b
Organization
2Kx36x8
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
BGA
Clock Freq (max)
166MHz
Supply Current
150mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72P51339L6BB8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72P51339L6BB8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
DESCRIPTION
trol devices are single chips with up to 32 discrete configurable FIFO queues.
All queues within the device have a common data input bus, (write port) and
a common data output bus, (read port). Data written into the write port is directed
to a specific queue via an internal de-multiplex operation, addressed by the write
address bus (WRADD). Data read from the read port is accessed from a specific
queue via an internal multiplex operation, addressed by the read address bus
(RDADD). Data writes and reads can be performed at high speeds up to
200MHz, with access times of 3.6ns. Data write and read operations are totally
independent of each other, a queue maybe selected on the write port and a
different queue on the read port or both ports may select the same queue
simultaneously.
for write and read operations respectively. Also a Programmable Almost Full
and Programmable Almost Empty flag for each queue is provided. Two 8 bit
programmable flag busses are available, providing status of queues not
selected for write or read operations. When 8 or less queues are configured
in the device these flag busses provide an individual flag per queue, when more
than 8 queues are used, either a Polled or Direct mode bus operation provides
the flag busses with all queues status.
36 bits wide. When Bus Matching is used the device ensures the logical transfer
of data throughput in a Little Endian manner.
ready flag output (PR) indicating when at least one (or more) packets of data
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
The IDT72P51339/72P51349/72P51359/72P51369 multi-queue flow-con-
The device provides Full flag and Empty flag status for the queue selected
Bus Matching is available on this device, either port can be 9 bits, 18 bits or
A packet mode of operation is also provided. Packet mode provides a packet
5
within a queue is available for reading. The Packet Ready indicator is generated
upon detection of the start and end of packet demarcation bits. The multi-queue
device then provides the user with an internally generated packet ready status
per queue.
to program the total number of queues between 1 and 32, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is
available that configures the device in a predetermined manner.
configuration/setup pins and must be performed before further programming of
the device can take place. On the rising edge of master reset the device operating
mode is set, the device programming mode (serial, parallel or default) is set and
the expansion configuration device type (master or slave) is set.
either 2.5V LVTTL, 1.5V HSTL or 1.8V eHSTL mode. The type of I/O is selected
via the IOSEL input. The core supply voltage (V
however the output levels can be set independently via a separate supply,
V
a fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
outline of the functional blocks within the device.
DDQ
The user has full flexibility configuring queues within the device, being able
A Master Reset must be provided to the device. A Master Reset latches in
The multi-queue flow-control device has the capability of operating its I/O in
A JTAG test port is provided, here the multi-queue flow-control device has
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an
.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DD
) to the multi-queue is 1.8V,
AUGUST 4, 2005