IDT89HPES24N3YCBXG IDT, Integrated Device Technology Inc, IDT89HPES24N3YCBXG Datasheet

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IDT89HPES24N3YCBXG

Manufacturer Part Number
IDT89HPES24N3YCBXG
Description
IC PCI SW 24LANE 3PORT 420-SBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT89HPES24N3YCBXG

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
89HPES24N3YCBXG

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Part Number
Manufacturer
Quantity
Price
Part Number:
IDT89HPES24N3YCBXG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Device Overview
Express® switching solutions offering the next-generation I/O intercon-
nect standard. The PES24N3 is a 24-lane, 3-port peripheral chip that
performs PCI Express Base switching with a feature set optimized for
high performance applications such as servers, storage, and communi-
cations/networking. It provides high-performance I/O connectivity and
switching functions between a PCIe® upstream port and two down-
stream ports or peer-to-peer switching between downstream ports.
Features
Block Diagram
© 2007 Integrated Device Technology, Inc.
The 89HPES24N3 is a member of IDT’s PRECISE™ family of PCI
– 24 PCI Express lanes (2.5Gbps), 3 switch ports
– Low latency cut-through switch architecture
– Supports 128 to 2048 byte maximum payload size
– Supports one virtual channel
– PCI Express Base specification Revision 1.0a compliant
– Port arbitration schemes utilizing round robin or weighted
– Supports automatic per port link with negotiation (x8, x4, x2, or
– Supports static lane reversal on all ports
– Supports polarity inversion
– Supports locked transactions, allowing use with legacy soft-
High Performance PCI Express Switch
Flexible Architecture with Numerous Configuration Options
round robin algorithms
x1)
ware
SerDes
Logical
Layer
Phy
Multiplexer / Demultiplexer
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
Frame Buffer
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
...
®
x8 Upstream Port and Two x8 Downstream Ports
SerDes
Logical
Layer
Phy
24-Lane 3-Port PCI Express®
Switch
Route Table
Figure 1 Internal Block Diagram
SerDes
24 PCI Express Lanes
Logical
Layer
Phy
Multiplexer / Demultiplexer
3-Port Switch Core
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
1 of 30
...
– Ability to load device configuration from serial EEPROM
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
– Integrates 24 2.5 Gbps embedded SerDes, 8B/10B encoder/
– Internal end-to-end parity protection on all TLPs ensures data
– Supports ECRC passed through
– Supports PCI Express Native Hot-Plug
– Supports Hot-Swap
– Supports PCI Power Management Interface specification,
– Unused SerDes are disabled
– Supports Advanced Configuration and Power Interface Speci-
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Arbitration
Highly Integrated Solution
Reliability, Availability, and Serviceability (RAS) Features
Power Management
Testability and Debug Features
SerDes
Logical
Layer
Port
Phy
queueing
decoder (no separate transceivers needed)
integrity even in systems that do not implement end-to-end
CRC (ECRC)
• Compatible with Hot-Plug I/O expanders used on PC moth-
Revision 1.1 (PCI-PM)
fication, Revision 2.0 (ACPI) supporting active link state
erboards
SerDes
Logical
Layer
Phy
Multiplexer / Demultiplexer
Scheduler
Transaction Layer
Data Link Layer
SerDes
Logical
Layer
Phy
...
89HPES24N3
December 18, 2007
SerDes
Data Sheet
Logical
Layer
Phy
DSC 6802

Related parts for IDT89HPES24N3YCBXG

IDT89HPES24N3YCBXG Summary of contents

Page 1

Device Overview The 89HPES24N3 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O intercon- nect standard. The PES24N3 is a 24-lane, 3-port peripheral chip that performs PCI Express Base switching with a ...

Page 2

IDT 89HPES24N3 Data Sheet ◆ Two SMBus Interfaces – Slave interface provides full access to all software-visible registers by an external SMBus master – Master interface provides connection for an optional serial EEPROM used for initialization – Master interface is ...

Page 3

IDT 89HPES24N3 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES24N3. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using ...

Page 4

IDT 89HPES24N3 Data Sheet Signal MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Signal GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] Type Name/Description I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information ...

Page 5

IDT 89HPES24N3 Data Sheet Signal CCLKDS CCLKUS MSMBSMODE PERSTN RSTHALT TSTRSVD SWMODE[3:0] Signal JTAG_TCK JTAG_TDI Type Name/Description I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream ...

Page 6

IDT 89HPES24N3 Data Sheet Signal JTAG_TDO JTAG_TMS JTAG_TRST_N Signal V CORE APE Type Name/Description O JTAG Data Output. This is the serial data shifted out from ...

Page 7

IDT 89HPES24N3 Data Sheet Pin Characteristics Note: Some input pads of the PES24N3 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if ...

Page 8

IDT 89HPES24N3 Data Sheet Function JTAG JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N Pin Name Type Buffer I LVTTL Table 7 Pin Characteristics (Part Internal I/O Type Notes Resistor STI pull-up pull-up ...

Page 9

IDT 89HPES24N3 Data Sheet Logic Diagram — PES24N3 Reference Clock PCI Express Switch SerDes Input Port A PCI Express Switch SerDes Input Port B PCI Express Switch SerDes Input Port C Master SMBus Interface SSMBADDR[5,3:1] Slave SMBus Interface System Pins ...

Page 10

IDT 89HPES24N3 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 12 and 13. Parameter Refclk Input reference clock frequency range FREQ 2 Refclk Duty cycle of input ...

Page 11

IDT 89HPES24N3 Data Sheet Parameter T Max time between jitter median & max deviation RX-EYE-MEDIUM TO MAX JITTER T Unexpected Idle Enter Detect Threshold Integration Time RX-IDLE-DET-DIFF- ENTER TIME T Lane to lane input skew RX-SKEW 1. Minimum, Typical, and ...

Page 12

IDT 89HPES24N3 Data Sheet JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N Recommended Operating Supply Voltages Symbol Parameter V CORE Internal logic supply DD V I/O I/O supply except for SerDes LVPECL/CML PCI Express Digital Power DD V APE PCI ...

Page 13

IDT 89HPES24N3 Data Sheet Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the PES24N3, the power-up sequence must be as follows I/O ...

Page 14

IDT 89HPES24N3 Data Sheet I/O Type Parameter Serial Link V Voltage change during receiver detection TX-RCV-Detect (cont.) RL Transmitter Differential Return loss TX-DIFF RL Transmitter Common Mode Return loss TX- Differential TX impedance TX-DEFF-DC Z Single ended TX ...

Page 15

IDT 89HPES24N3 Data Sheet I/O Type Parameter Leakage Inputs I/O / LEAK W O Pull-ups/downs I/O LEAK WITH Pull-ups/downs 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a. 1 Description Min — — — Table 15 ...

Page 16

IDT 89HPES24N3 Data Sheet Package Pinout — 420-BGA Signal Pinout for PES24N3 The following table lists the pin numbers and signal names for the PES24N3 device. Pin Function Alt Pin B10 ...

Page 17

IDT 89HPES24N3 Data Sheet Pin Function Alt Pin F23 F24 V APE K5 DD F25 V CORE K22 DD F26 V CORE K23 DD G1 PEBTN07 K24 G2 PEBTP07 K25 K26 DD G4 PEBRN07 ...

Page 18

IDT 89HPES24N3 Data Sheet Pin Function Alt Pin AA5 PEBRP00 AC3 AA22 PECRP07 AC4 AA23 PECRN07 AC5 AA24 V PE AC6 DD AA25 PECTP07 AC7 AA26 PECTN07 AC8 AB1 V AC9 SS AB2 V AC10 SS AB3 V CORE AC11 ...

Page 19

IDT 89HPES24N3 Data Sheet Power Pins V Core V Core C14 F25 C16 F26 M26 D8 P1 D10 P26 D12 T1 D13 T26 D15 V1 D17 V26 D18 AB3 D19 AB4 D21 AB5 ...

Page 20

IDT 89HPES24N3 Data Sheet Ground Pins A24 A25 A26 B1 B2 B25 B26 C10 C12 C18 C20 C22 C24 C25 D11 F23 ...

Page 21

IDT 89HPES24N3 Data Sheet Alternate Signal Functions Signals Listed Alphabetically Signal Name CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_03 GPIO_04 GPIO_05 GPIO_06 GPIO_07 JTAG_TCK JTAG_TDI JTAG_TMS JTAG-TDO JTAG-TRST_N MSMBADDR_1 MSMBADDR_2 MSMBADDR_3 MSMBADDR_4 MSMBCLK MSMBDAT MSMBSMODE Pin GPIO Alternate B19 GPIO[2] IOEXPINTN ...

Page 22

IDT 89HPES24N3 Data Sheet Signal Name PEALREV PEARN00 PEARN01 PEARN02 PEARN03 PEARN04 PEARN05 PEARN06 PEARN07 PEARP00 PEARP01 PEARP02 PEARP03 PEARP04 PEARP05 PEARP06 PEARP07 PEATN00 PEATN01 PEATN02 PEATN03 PEATN04 PEATN05 PEATN06 PEATN07 PEATP00 PEATP01 PEATP02 PEATP03 PEATP04 PEATP05 PEATP06 PEATP07 PEBLREV ...

Page 23

IDT 89HPES24N3 Data Sheet Signal Name PEBRN02 PEBRN03 PEBRN04 PEBRN05 PEBRN06 PEBRN07 PEBRP00 PEBRP01 PEBRP02 PEBRP03 PEBRP04 PEBRP05 PEBRP06 PEBRP07 PEBTN00 PEBTN01 PEBTN02 PEBTN03 PEBTN04 PEBTN05 PEBTN06 PEBTN07 PEBTP00 PEBTP01 PEBTP02 PEBTP03 PEBTP04 PEBTP05 PEBTP06 PEBTP07 PECLREV PECRN00 PECRN01 PECRN02 ...

Page 24

IDT 89HPES24N3 Data Sheet Signal Name PECRN05 PECRN06 PECRN07 PECRP00 PECRP01 PECRP02 PECRP03 PECRP04 PECRP05 PECRP06 PECRP07 PECTN00 PECTN01 PECTN02 PECTN03 PECTN04 PECTN05 PECTN06 PECTN07 PECTP00 PECTP01 PECTP02 PECTP03 PECTP04 PECTP05 PECTP06 PECTP07 PEREFCLKN1 PEREFCLKN2 PEREFCLKP1 PEREFCLKP2 PERSTN REFCLKM RSTHALT ...

Page 25

IDT 89HPES24N3 Data Sheet Signal Name SSMBADDR_1 SSMBADDR_2 SSMBADDR_3 SSMBADDR_5 TSTRSVD SSMBCLK SSMBDAT SWMODE_0 SWMODE_1 SWMODE_2 SWMODE_3 V CORE APE I/O Type Location ...

Page 26

IDT 89HPES24N3 Data Sheet PES24N3 Pinout — Top View ...

Page 27

IDT 89HPES24N3 Data Sheet PES24N3 Package Drawing — 420-Pin BX420/BXG420 December 18, 2007 ...

Page 28

IDT 89HPES24N3 Data Sheet PES24N3 Package Drawing — Page Two December 18, 2007 ...

Page 29

IDT 89HPES24N3 Data Sheet Revision History July 18, 2006: Publication of YC data sheet. April 4, 2007: In Table 2, revised description for MSMBCLK signal to include “active only when EEPROM data is being loaded.” November 14, 2007: Added new ...

Page 30

IDT 89HPES24N3 Data Sheet Ordering Information A AAA NN Product Operating Device Family Family Voltage Valid Combinations 89HPES24N3YCBX 420-pin BX420 package, Commercial Temperature 89HPES24N3YDBX 420-pin BX420 package, Commercial Temperature 89HPES24N3YCBXG 420-pin Green BX420 package, Commercial Temperature 89HPES24N3YDBXG 420-pin Green BX420 ...

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