IDT89HPES24N3YCBXG IDT, Integrated Device Technology Inc, IDT89HPES24N3YCBXG Datasheet - Page 2

• Manufacturer Part Number: IDT89HPES24N3YCBXG
• Description: IC PCI SW 24LANE 3PORT 420-SBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES24N3YCBXG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES24N3YCBXG

Product Description
the most efficient high-performance I/O connectivity solution for applica-
tions requiring high throughput, low latency, and simple board layout
with a minimum number of board layers. It provides 12 GBps (96 Gbps)
of aggregated, full-duplex switching capacity through 24 integrated
serial lanes, using proven and robust IDT technology. Each lane
provides 2.5 Gbps of bandwidth in both directions and is fully compliant
with PCI Express Base specification 1.0a.
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 1.0a. The PES24N3 can operate either as a store and forward
or cut-through switch depending on the packet size and is designed to
switch memory and I/O transactions. It supports eight Traffic Classes
(TCs) and one Virtual Channel (VC) with sophisticated resource
management. This includes system selectable algorithms such as round
robin, weighted round-robin, and strict priority schemes guaranteeing
bandwidth allocation and/or latency for critical traffic classes in applica-
tions such as high throughput 10 Gigabit I/Os, SATA controllers, and
Fibre Channel HBAs.
Switch Configuration
lanes. Each of the three ports is statically allocated 8 lanes with ports
labeled as A, B and C. Port A is always the upstream port while ports B
and C are always downstream ports. The switch operating mode, as well
as an optional initialization from a serial EEPROM, is selected via the
Switch Mode (SWMODE[3:0]) inputs.
PES24N3 port is capable of independently negotiating to a x8, x4, x2 or
x1 width. Thus, the PES24N3 may be used in virtually any three port
switch configuration (e.g., {x8, x8, x8}, {x4, x4, x4}, {x4, x2, x1}, etc.).
The PES24N3 supports static lane reversal. For example, lane reversal
for upstream port A may be configured by asserting the PCI Express
Port A Lane Reverse (PEALREV) input signal or through serial
EEPROM or SMBus initialization. Lane reversal for ports B and C may
be enabled via a configuration space register, serial EEPROM, or the
SMBus.
IDT 89HPES24N3 Data Sheet
Utilizing standard PCI Express interconnect, the PES24N3 provides
The PES24N3 is based on a flexible and efficient layered architec-
The PES24N3 is a three port switch that contains 24 PCI Express
During link training, link width is automatically negotiated. Each
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– Slave interface provides full access to all software-visible
– Master interface provides connection for an optional serial
– Master interface is also used by an external Hot-Plug
– Master and slave interfaces may be tied together so the
Two SMBus Interfaces
8 General Purpose Input/Output pins
Packaged in 27x27mm 420 ball BGA with 1mm ball spacing
registers by an external SMBus master
EEPROM used for initialization
I/O expander
PES24N3 can act as both master and slave
2 of 30
PCI Express
PES24N3
Slots
Figure 2 I/O Expansion Application
10GbE
I/O
Processor
PES24N3
Bridge
North
10GbE
I/O
SATA
I/O
Memory
December 18, 2007
Memory
PES24N3
Memory
Memory
SATA
I/O