IDT72V51556L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51556L7-5BB8 Datasheet - Page 46

• Manufacturer Part Number: IDT72V51556L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51556L7-5BB8

• Configuration: Dual
• Density: 2Mb
• Access Time (max): 4ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51556L7-5BB8

NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
Cycle:
*A* Queue 30 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs.
*C* The PAE flag output now switches to device 1. Word, Wn is read from Q30 due to the FWFT operation. This read operation from Q30 is at the almost empty boundary, therefore
*D* Q15 of device 1 is selected.
*E* The PAE flag goes LOW due to the read from Q30 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*F* Word, W0 is read from Q15 due to the FWFT operation. The PAE flag goes HIGH to show that Q15 is not almost empty.
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
WCLK
RDADD
RADEN
PAE
(Device 1)
PAE
(Device 2)
RCLK
WEN
REN
from at the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + t
De-assertion: t
If t
RCLK
PAE
PAE will go LOW 2 RCLK cycles later.
Qout
REN
SKEW2
is violated there will be one extra RCLK cycle.
HIGH
HIGH-Z
HIGH-Z
SKEW2
t
t
CLKH
AS
t
QS
+ RCLK + t
D
RAE
t
ENS
*A*
n+1 words in Queue
1
Q
t
CLKL
30
t
QH
RAE
t
AH
t
ENH
t
SKEW2
*B*
Figure 24. Almost Empty Flag Timing and Queue Switch
t
RAE
t
OLZ
Figure 25. Almost Empty Flag Timing
*C*
t
A
t
AEHZ
t
AELZ
t
t
AS
QS
HIGH-Z
D
46
*D*
1
Q
t
15
D
ENS
1
t
QH
t
Q
AH
30
W
n+2 words in Queue
n
*E*
t
ENH
t
A
t
RAE
D
1
Q
1
30
W
*F*
COMMERCIAL AND INDUSTRIAL
n+1
t
A
t
t
RAE
RAE
TEMPERATURE RANGES
D
1
Q
15
2
*G*
W
0
n+1 words in Queue
t
A
D
1
Q
5904 drw25
5904 drw27
15
W
1