IDT72V51556L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51556L7-5BB8 Datasheet - Page 9

• Manufacturer Part Number: IDT72V51556L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51556L7-5BB8

• Configuration: Dual
• Density: 2Mb
• Access Time (max): 4ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51556L7-5BB8

PIN DESCRIPTIONS (CONTINUED)
IDT72V51546/72V51556 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
OV
(P9)
OW
(L16)
PAE
(P10)
PAEn/PRn
(See Pin No.
table for details) Bus/Packet Ready
PAF
(R8)
PAFn
(See Pin No.
table for details) Bus
PKT
(J14)
PR
(R9)
Symbol &
Pin No.
(1)
(1)
Output Valid Flag
Output Width
Programmable
Almost-Empty Flag OUTPUT for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
Programmable
Almost-Empty Flag OUTPUT Almost Empty mode or Packet mode. This output bus provides PAE/ PRn status of 8 queues (1 quadrant),
Flag Bus
Programmable
Almost-Full Flag
Programmable
Almost-Full Flag
Packet Mode
Packet Ready Flag
Name
OUTPUT device data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay.
OUTPUT operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected queue is
OUTPUT 8 queues (1 quadrant), within a selected device, having a total of 4 quadrants. During Queue read/write
OUTPUT for read operations. During a master reset the state of the PKT input determines whether Packet mode
I/O TYPE
LVTTL
LVTTL
INPUT
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
INPUT
LVTTL
operations these outputs provide programmable full flag status, in either direct or polled mode. The mode
providing both a Packet Ready (PR) output and a Programmable Almost Empty (PAE) discrete output,
If packet mode has been selected this flag output provides Packet Ready status of the queue selected
This output flag provides output valid status for the data word present on the multi-queue flow-control
That is, there is a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time the
OV flag represents the data in that respective queue. When a selected queue on the read port is read to
empty, the OV flag will go HIGH, indicating that data on the output bus is not valid. The OV flag also has
High-Impedance capability, required when multiple devices are used and the OV flags are tied together.
This pin is setup during Master Reset and must not toggle during any device operation. This pin is used
in conjunction with IW and BM to setup the data input and output bus widths to be a combination of x9, x18
or x36, (providing that one port is x36).
This pin provides the Almost-Empty flag status for the queue that has been selected on the output port
queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is
synchronized to RCLK.
On the 32Q device the PAEn/ PRn bus is 8 bits wide. During a Master Reset this bus is setup for either
provide programmable empty flag status or packet ready status, in either direct or polled mode. The mode
of flag operation is determined during master reset via the state of the FM input. This flag bus is capable
of High-Impedance state, this is important during expansion of multi-queue devices. During direct operation
the PAEn/PRn bus is updated to show the PAE/PR status of a quadrant of queues within a selected device.
Selection is made using RCLK, ESTR and RDADD. During Polled operation the PAEn/PRn bus is loaded
with the PAE/ PRn status of multi-queue flow-control quadrants sequentially based on the rising edge
of RCLK. PAE or PR operation is determined by the state of PKT during master reset.
This pin provides the Almost-Full flag status for the queue that has been selected on the input port for write
almost-full. This flag output may be duplicated on one of the PAFn bus lines. This flag is synchronized to WCLK.
On the 32Q device the PAFn bus is 8 bits wide. At any one time this output bus provides PAF status of
of flag operation is determined during master reset via the state of the FM input. This flag bus is capable
of High-Impedance state, this is important during expansion of multi-queue devices. During direct operation
the PAFn bus is updated to show the PAF status of a quadrant of queues within a selected device.
Selection is made using WCLK, FSTR, WRADD and WADEN. During Polled operation the PAFn bus is
loaded with the PAF status of multi-queue flow-control quadrants sequentially based on the rising edge
of WCLK.
The state of this pin during a Master Reset will determine whether the part is operating in Packet mode
or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part will operate
in packet mode, if it is LOW then almost empty mode. If packet mode has been selected the read port flag
bus becomes packet ready flag bus, PRn and the discrete packet ready flag, PR is functional. If almost
empty operation has been selected then the flag bus provides almost empty status, PAEn and the discrete
almost empty flag, PAE is functional, the PR flag is inactive and should not be connected. Packet Ready
utilizes user marked locations to identify start and end of packets being written into the device. Packet Mode
can only be selected if both the input port width and output port width are 36 bits.
of operation will be used. If Packet mode is selected, then the condition of the PR flag and OV signal are
asserted indicates a packet is ready for reading. The user must mark the start of a packet and the end of
a packet when writing data into a queue. Using these Start Of Packet (SOP) and End Of Packet (EOP)
markers, the multi-queue device sets PR LOW if one or more “complete” packets are available in the queue.
A complete packet(s) must be written before the user is allowed to switch queues.
within a selected device, having a total of 4 quadrants. During Queue read/write operations these outputs
9
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES