IDT88P8342BHGI IDT, Integrated Device Technology Inc, IDT88P8342BHGI Datasheet - Page 65

• Manufacturer Part Number: IDT88P8342BHGI
• Description: IC SPI3-SPI4 EXCHANGE 820-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT88P8342BHGI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 88P8342BHGI

3 ingress per-LID free segment backpressure threshold based on the number
of free buffer segments (M) available, as follows:
a LID at the time of backpressure initiation.
9.3.10 Block base 0x1300 registers
control registers are at Block_Base 0x1300.
SPI-3 to SPI-4 PFP register (Block_base 0x1300 +
Register_offset 0x00)
TABLE 76 - SPI-3 TO SPI-4 PFP REGISTER
(REGISTER_OFFSET 0x00)
has read and write access. There is one SPI-3 to SPI-4 PFP Register per SPI-
3 ingress. The bit fields of a SPI-3 to SPI-4 PFP Register are described.
interface that will ever be used is programmed into the NR_LID field. Once
configured after reset, this value can not be changed. Fewer LIDs can be used
by not activating some of the LIDs, but more LIDs than the value in NR_LID are
not allowed and will generate an error. The NR_LID field is important, as the
buffer segment pool is divided among the number of LIDs programmed into the
NR_LID field.
the SPI-4 egress is available for each SPI-3 physical port. A configurable part
of this buffer segment pool can be assigned to each of the possible LIDs allowed
by the NR_LID field value per SPI-3 physical interface. The buffer size for a LID
can be configured in multiples (M) of 256 bytes. Modifications of the buffer size
allocated to a LID are supported only when the logical port associated to the LID
is disabled. Attempts to allocate more memory than available will generate an
allocation error event. The indirect access module will discard the attempt.
segments. Each buffer segment is equal to 256 bytes. The buffer segments are
shared among the number of logical ports defined by the static NR_LID
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
FREE_SEGMENT The FREE_SEGMNET field is used to define the SPI-
THRESHOLD = N * FREE_SEGEMENT,
Where the value of N is defined as a function of the domain of M:
The THRESHOLD thus defined is the number of free segments available for
The SPI-3 ingress to SPI-4 egress Packet Fragment Processor and flow
A SPI-3 ingress to SPI-4 egress PFP (Packet Fragment Processor) Register
NR_LID The maximum number of LIDs per SPI-3 physical ingress
A 128 Kbyte SPI-3 to SPI-4 buffer segment pool for storing data bursts for
A 128 Kbyte SPI-3 to SPI-4 buffer segment pool is divided into 508 buffer
NR_LID
Reserved
Field
0x1FC to 0x100
0x0FF to 0x080
0x07F to 0x040
0x03F to 0x020
0x01F to 0x000
M[8:0]
Bits
2:0
7:3
N (base 10)
Length
3
5
16
8
4
2
1
Initial Value
0b011
0x0
65
configuration. The buffer segments do not have to be equally shared among
the LIDs. One buffer segment corresponds to a data burst to be forwarded to
the SPI-4 egress interface.
interface that will never have more than four LIDs, set the NR_LID field for this
interface to 0x01. This allows 256 buffer segments for a LID, with the total number
of buffer segments for all 4 LIDs equal to 508. Let’s say you want only 64 buffer
segments for one of the LIDs. Program field M for that LID to 0x040 (64 base
10). Let’s say you want to backpressure the SPI-3 ingress interface when 48
of the 64 allocated buffers for this LID are full. In other words, you want to exert
SPI-3 ingress backpressure when only 16 segments remain for this LID. Since
M=0x040, N=4 from the description of the M field above [Block_base 0x1200].
Setting the FREE_SEGMENT field to 4 then yields the desired THRESHOLD
of 16.
TABLE 77 - NR_LID FIELD ENCODING
SPI-3 to SPI-4 flow control register (Block_base
0x1300 + Register_offset 0x01)
TABLE 78 - SPI-3 TO SPI-4 FLOW CONTROL REG-
ISTER (REGISTER_OFFSET 0x01)
one SPI-3 to SPI-4 flow control register per SPI-3 ingress.The bit fields of the
SPI-3 to SPI-4 flow control register are described.
interpreted as status or credit information as selected by the CREDIT_EN flag
in the SPI-3 to SPI-4 flow control Register. If the status mode is used, data will
be egressed until the status is changed by the attached device. If the credit mode
is used, the SPI-4 egress will issue only one credit’s worth data burst and then
wait for another credit from the status channel before issuing another LID burst.
to an LP. This feature is included to relieve systems with long latency between
updates. When this feature is not enabled, only one burst per LP is allowed into
the SPI-4 egress buffers.
CREDIT_EN
BURST_EN
Reserved
An example of the use of the buffer segment pool follows. For a SPI-3 ingress
A SPI-3 to SPI-4 flow control register has read and write access. There is
CREDIT_EN
BURST_EN
NR_LID
0b000
0b001
0b010
0b011
0b100
0b101
Field
0=Status mode
1=Credit mode
0=Disable burst enable
1=Enable burst enable
Maximum Number
of LIDs
The information received over the FIFO status channel is
Multiple Burst Enable allows more than one burst to be sent
16
32
64
1
4
8
Bits
7:3
INDUSTRIAL TEMPERATURE RANGE
0
1
Length
Maximum Buffer Segments
for a LID
1
1
6
508
256
128
64
32
16
APRIL 10, 2006
Initial Value
0x00
0b1
0b0