IDT88P8342BHGI IDT, Integrated Device Technology Inc, IDT88P8342BHGI Datasheet - Page 77

• Manufacturer Part Number: IDT88P8342BHGI
• Description: IC SPI3-SPI4 EXCHANGE 820-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT88P8342BHGI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 88P8342BHGI

9.4.10 Common module block base 0x0900 registers
PMON timebase control register (Block_base
0x0900 + Register_offset 0x00)
TABLE 119 - PMON TIMEBASE CONTROL REGIS-
TER (REGISTER_OFFSET 0x00)
timebase module directs a timebase event to all PMON modules in the device.
The timebase period can be internally or externally generated. The selection
is made by the INTERNAL flag in the PMON update control register. A snapshot
of the counters is taken when the timebase expires and the counters are cleared.
The PMON update control register is at common module 0x8000 + Block_base
0x0900 + Register_offset 0x00 = 0x8900 and has read and write access.
mance monitoring. The internal timebase is either generated by the internal
processor or by a free running timer. The selection is made by the TIMER flag
in the PMON update control register. When the time interval expires, the
TIMEBASE pin is asserted for sixteen MCLK cycles. The timebase event is
captured by the timebase status in the support interrupt status register.
generated timebase signal is applied to the TIMEBASE pin. A positive edge
detector generates the timebase event.
pin is driven high for sixteen MCLK cycles.
cessor-controlled write to generate the timebase event. The TIMER field is valid
only when the INTERNAL field is a logic one.
by a write access with a logical one to the MANUAL flag in the PMON Update
Control Register if the microprocessor timebase is selected. The MANUAL bit
is self-clearing. The MANUAL field is only valid if the TIMER field is a logic zero.
Timebase register (Block_base 0x0900 +
Register_offset 0x01)
TABLE 120 - TIMEBASE REGISTER
(REGISTER_OFFSET 0x01)
has read and write access.
in the timebase register. The PERIOD field specifies the number of MCLK clock
cycles required for a single event. The PERIOD field is only valid if both the
INTERNAL and TIMER fields are a logic one.
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INTERNAL
TIMER
MANUAL
A single PMON timebase module is available in the IDT88P8344. The PMON
INTERNAL
0= External timebase from the TIMEBASE pin is selected. The externally
1=Internal timebase is selected. When the time interval expires, the TIMEBASE
TIMER Selects between the internal free-running timebase or a micropro-
MANUAL
The timebase register is at Block_base 0x0900 + Register_offset 0x01 and
The timebase period for free-running timers is configured by the PERIOD field
PERIOD
Field
Field
0=Selects the microprocessor generated timebase
1=Selects the internal free-running timebase
0=No operation
1=A timebase event is generated
Selects between internal or external timebases for perfor-
The microprocessor generates an internal timebase event
Bits
26:0
Bits
0
1
2
Length
Length
27
1
1
1
Initial Value
Initial Value
0x4A2 8600
0b0
0b0
0b0
77
TABLE 122 - OCLK AND MCLK FREQUENCY
SELECT ENCODING
Clock generator control register (Block_base
0x0900 + Register_offset 0x010)
TABLE 121 - CLOCK GENERATOR CONTROL
REGISTER (REGISTER_OFFSET 0x10)
0x0900 + Register_offset 0x010.
MCLK for internal use, and SPI-4 data and FIFO status channel egress clocks.
The OCLK[3:0] clock frequencies can be selected independently of each other.
OCLK[3:0] outputs can be used as SPI-3 clock sources. The OCLK[3:0] pins
are separately enabled by setting each associated enable flag in Table 121 -
Clock generator control register (Register_offset 0x10). When an OCLK[3:0]
output is not enabled, it is in a logic low state. MCLK is the internal processing
clock, and is always enabled. Refer to Table 122 - OCLK and MCLK frequency
select encoding, for selecting the frequencies of MCLK and OCLKs.
low. Immediately following reset, all OCLK[3:0] outputs are active with the output
frequency defined by pll_oclk divided by the initial value in the Table 121 - Clock
generator control register (Block_base 0x0900 + Register_offset 0x10).
write access. The clock generator control register is used to set the frequency
of MCLK and the OCLK outputs, as well as to enable the OCLK outputs. Note
that divider values should be chosen so that OCLK[3:0] and MCLK are within
their specified operating range provided in Table 136, OCLK[3:0] clock outputs
and MCLK internal clock.
OCLK and MCLK frequency select encoding.
and MCLK frequency select encoding.
The clock generator control register is at common module Block_base
The clock generator provides four clock outputs on the OCLK[3:0] pins,
During either a hardware or a software reset, the OCLK[3:0] pins are all logic
The clock generator control register at indirect address 0x8910 has read and
OCLK[k]_EN
0=OCLK[k] is not enabled and OCLK[k] is at a logic zero
1=OCLK[k] is enabled and active
N_OCLK[k] [1:0] Select the OCLK[k] frequency according to Table 122-
N_MCLK[k] Select the MCLK frequency according to Table 122-OCLK
N_MCLK & N_OCLK[k] Frequency Selects
OCLK0_EN
N_OCLK0
Reserved
OCLK1_EN
N_OCLK1
Reserved
OCLK2_EN
N_OCLK2
Reserved
OCLK3_EN
N_OCLK3
Reserved
N_MCLK
Reserved
Field
Used for enabling the kth OCLK output
00
01
10
11
14:13
16:15
18:17
31:19
Bits
10:9
2:1
6:5
11
12
0
3
4
7
8
INDUSTRIAL TEMPERATURE RANGE
Length
13
1
2
1
1
2
1
1
2
1
1
2
2
2
pll_oclk / 4
pll_oclk / 6
pll_oclk / 8
pll_oclk / 10
APRIL 10, 2006
Frequency
Initial Value
0b01
0b11
0b11
0b11
0b11
0b11
0b0
0b1
0b0
0b1
0b0
0b1
0b0
0