IDT88P8344BHGI IDT, Integrated Device Technology Inc, IDT88P8344BHGI Datasheet - Page 36

• Manufacturer Part Number: IDT88P8344BHGI
• Description: IC SPI3-SPI4 EXCHANGE 820-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT88P8344BHGI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 88P8344BHGI

4.4.3 Microprocessor interface to SPI-4 egress
datapath
following is a description of the path taken by a burst of data through the device.
microprocessor interface. The data available bit is set. Data is stored in the insert
buffer along with the LP address, LID, error information, SOP, and EOP. Data
is stored in per-LID allocated buffer segments. The Table 36-SPI-3 data insert
control register is consulted, and determines to send this LID to the SPI-4 egress
port. The SPI-4 Packet Fragment Processor chooses the next LP. Data is sent
to the SPI-4 egress buffer along with the SPI-4 LP address, error information,
SOP, and EOP. Data is transmitted in bursts over the SPI-4 egress interface.
microprocessor data insert interface to the SPI-4 egress interface.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
Packets can be inserted into the SPI-3-4 datapath by the microprocessor. The
Data and control information are written to the insert buffer through the
The diagram below shows the datapath through the device from the
Min: 19.44MHz
Max: 133MHz
8 bit / 32 bit
4 x SPI-3
Figure 27. Microprocessor data insert interface to SPI-4 egress datapath
t+1
t
t+258
SOP
7
JTAG
LID Counters Memory
Figure 26. Microprocessor data insert buffer
data[255]
data[2]
data[1]
data[0]
length
flags
uproc
lid
SPI-3 /
LID map
Memory
EA
Main
A
ED
36
PAR
Chip Counters Memory
packet burst. Refer to Figure 26, Microprocessor data insert buffer for the data
format in the buffer. The microprocessor must verify the DATA_AVAILABLE flag
in the SPI-4 insert control register and waits until the flag is cleared. The
microprocessor specifies the EOP, SOP, ERROR, LID and LENGTH fields and
writes up to 256 bytes of packet fragment burst into the insert buffer. The packet
burst insert buffer is accessed through the Table 34, SPI-4 data insert register
(register_offsets 0x03, 0x0B, 0x13, 0x1B) SPI-4 data insert register. The
microprocessor hands over control of the buffer setting the DATA_AVAILABLE
flag in the SPI-4 insert control register. A SPI4_insert_empty event is generated
when the DATA_AVAILABLE flag is cleared. The event is directed towards the
interrupt module.
The microprocessor needs to write data into a dedicated buffer to insert a
EOP
0
t+1
t
t+258
SPI-4 /
LID map
EA
ED
PAR
6370 drw18
address parity error
data parity error
packet error
not used
Max:400 MHz
Min: 80 MHz
INDUSTRIAL TEMPERATURE RANGE
6370 drw28
SPI-4.2
APRIL 10, 2006