IDT88P8344BHGI IDT, Integrated Device Technology Inc, IDT88P8344BHGI Datasheet - Page 59

• Manufacturer Part Number: IDT88P8344BHGI
• Description: IC SPI3-SPI4 EXCHANGE 820-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT88P8344BHGI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 88P8344BHGI

an LP.
of the SPI-3 interface on a per-LP basis.
9.3.4 Block base 0x0700 registers
SPI-3 egress configuration register (Block_base
0x0700 + Register_offset 0x00)
TABLE 55 - SPI-3 EGRESS CONFIGURATION
REGISTER (REGISTER_OFFSET=0x00)
SPI-3 egress configuration registers have read and write access. A SPI-3
egress configuration registers is used to control the poll sequence length of a
SPI-3 egress interface when the SPI-3 interface is in Link mode. The SPI-3
egress configuration register is used to add two cycles to STX or EOP as
required to interface to the attached device.
sequence is from the LP associated with LID0 to the LP associated with the LID
for POLL_LENGTH - 1.
dummy STX cycles to a SPI-3 egress interface to meet the needs of an attached
device.
dummy EOP cycles to a SPI-3 egress interface to meet the needs of an attached
device.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
Reserved
STX_SPACING
EOP_SPACING
Reserved
POLL_LENGTH
ENABLE
BIT_REVERSAL This bit is used to reverse the bit ordering of each byte
There is one SPI-3 egress configuration register per SPI-3 interface. The
POLL_LENGTH Poll sequence length when in Link mode. The poll
STX_SPACING This bit is used to enable or disable the adding of two
EOP_SPACING This bit is used to enable or disable the adding of two
Field
0=LP disabled
1=LP enabled
0=Disable bit reversal for an LP
1=Enable bit reversal for an LP
0= No dummy STX cycles are added to a SPI-3 egress.
1= Two dummy STX cycles are added to a SPI-3 egress
0= No dummy EOP cycles are added to a SPI-3 egress.
1= Two dummy EOP cycles are added to a SPI-3 egress
This bit is used to enable or disable the connection of a LID to
31:10
Bits
5:0
7:6
8
9
Length
22
6
2
1
1
Initial Value
0x0F
0b00
0x00
0b0
0b0
59
SPI-4 ingress to SPI-3 egress flow control register
(Block_base 0x0700 + Register_offset 0x01)
TABLE 56 - SPI-4 INGRESS TO SPI-3 EGRESS FLOW
CONTROL REGISTER (REGISTER_OFFSET=0x01)
access. The bit fields of the SPI-4 ingress to SPI-3 egress flow control register
are described.
the attached SPI-3 device is interpreted as status or credit information as selected
by the CREDIT_EN bit in the SPI-4 ingress to SPI-3 egress flow control Register.
If the status mode is used, data will be egressed until the status is changed by
the attached SPI-3 device. If the credit mode is used, the SPI-3 egress will
transmit only one packet fragment and then wait for an update in the internal buffer
segment pool status before sending another packet fragment.
to an LP. When this feature is not enabled, only one burst per LP is allowed into
the SPI-3 egress buffers.
transferred to a SPI-3 egress buffers of the same port. This mode is useful for
off-line diagnostics.
SPI-3 egress test register (Block_base 0x0700 +
Register_offset 0x02)
TABLE 57 - SPI-3 EGRESS TEST REGISTER
(REGISTER_OFFSET=0x02)
parity error is introduced on a SPI-3 egress LP through the ADD_PAR_ERR
bit field. A single data parity error is introduced on a SPI-3 egress LP through
the DAT_PAR_ERR bit field. The LP affected by these two parity error bit fields
is enumerated in the PORT_ADDRESS field. The bit fields of SPI-3 egress test
register are described. The bit fields are automatically cleared following the
generation of the associated error.
CREDIT_EN
BURST_EN
LOOP_BACK
Reserved
ADD_PAR_ERR
DAT_PAR_ERR
Reserved
PORT_ADDRESS
The SPI-4 ingress to SPI-3 egress flow control register has read and write
CREDIT_EN
BURST_EN
LOOP_BACK
The SPI-3 egress test register has read and write access. A single address
Field
Field
0=Status mode
1=Credit mode
0=Disable burst enable
1=Enable burst enable
0=Disable loopback
1=Enable loopback
CREDIT_EN The flow control information received from
Multiple Burst Enable allows more than one burst to be sent
In this mode the contents of a SPI-3 ingress are directly
Bits
31:3
Bits
15:8
7:2
1
2
0
0
1
INDUSTRIAL TEMPERATURE RANGE
Length
Length
1
1
8
6
29
1
1
1
Initial Value
Initial Value
APRIL 10, 2006
0x00
0x0F
0x00
0b0
0b0
0b0
0b0
0b0