IDT89TTM553BL IDT, Integrated Device Technology Inc, IDT89TTM553BL Datasheet - Page 5

• Manufacturer Part Number: IDT89TTM553BL
• Description: IC TRAFFIC MANAGER 960-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89TTM553BL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89TTM553BL

IDT 89TTM553
BXT_WR_N
BXT_DOUT[3:0]
BXT_LLT_VREF
FCT_CLK_CP,
FCT_CLK_CN
FCT_CLK_KP,
FCT_CLK_KN
FCT_ADDR[19:0]
FCT_RD_N
FCT_DIN[27:0]
FCT_WR_N
FCT_DOUT[27:0]
FCT_VREF[1:0]
FPT_CLK_CP,
FPT_CLK_CN
FPT_CLK_KP,
FPT_CLK_KN
FPT_ADDR[20:0]
FPT_RD_N
Signal Name
Signal Name
Signal Name
1.5V HSTL Class 1
1.5V HSTL Class 1
0.75V
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
0.75
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
I/O Type
I/O Type
I/O Type
Table 2 Buffer Linked List Extension QDR SRAM (Part 2 of 2)
Table 4 Flow Parameters Table QDR SRAM (Part 1 of 2)
Table 3 Flow Control Table QDR SRAM
Dir.
Dir.
Dir.
—
—
O
O
O
O
O
O
O
O
O
O
I
I
I
5 of 30
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
Freq.
Freq.
Freq.
—
—
asserted, a write cycle is initiated to the external QDR SRAM
devices.
nized to the K and K# during write operations
HSTL reference. Nominally V
FCT QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
FCT QDR SRAM output clock: This clock pair times the con-
trol outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
FCT QDR SRAM address outputs.
asserted, a read cycle is initiated to the external QDR SRAM
devices.
hold times around the rising edges of C and C# during read
operations
asserted, a write cycle is initiated to the external QDR SRAM
devices.
nized to the K and K# during write operations
HSTL reference. Nominally V
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
trol outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
asserted, a read cycle is initiated to the external QDR SRAM
devices.
BXT QDR SRAM synchronous write output (active low): When
BXT QDR SRAM write data outputs: Output data is synchro-
FCT QDR SRAM synchronous read output (active low): When
FCT QDR SRAM data inputs: Input data must meet setup and
FCT QDR SRAM synchronous write output (active low): When
FCT QDR SRAM write data outputs: Output data is synchro-
FPT QDR SRAM input clock: This clock pair registers data
FPT QDR SRAM output clock: This clock pair times the con-
FPT QDR SRAM address outputs.
FPT QDR SRAM synchronous read output (active low): When
Remarks
Remarks
Remarks
DDQ
DDQ
/ 2, so connect to 0.75 V
/ 2, so connect to 0.75 V
March 3, 2005