DS1961S-F3 Maxim Integrated Products, DS1961S-F3 Datasheet
DS1961S-F3
Specifications of DS1961S-F3
Related parts for DS1961S-F3
DS1961S-F3 Summary of contents
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... Apparatus: Approved Under Entity Concept for use in Class I, Division 1, Groups and D Locations (Application Pending) F5 MicroCan 0.36 ® Protocol IO F3 MicroCan 0.36 IO GND All dimensions are shown in millimeters DS1961S With SHA-1 Engine 5.89 0.51 © 1993 16.25 YYWW REGISTERED 17.35 000000FBD8B3 GND 3.10 0.51 © ...
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... ORDERING INFORMATION DS1961S-F5 F5 iButton DS1961S-F3 F3 iButton iButton DESCRIPTION The DS1961S combines 1024 bits of EEPROM, a 64-bit secret, an 8-byte register/control page with up to five user-read/write bytes, a 512-bit SHA-1 engine, and a fully featured 1-Wire interface in a rugged iButton. Data is transferred serially through the 1-Wire protocol, which requires only a single data lead and a ground return ...
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... Register Page 64-BIT LASERED ROM Each DS1961S contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits (see Figure 3). The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4 ...
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... ROM Function Commands (See Figure 9) DS1961S-Specific Memory Function Commands (See Figure 7) Figure 3. 64-BIT LASERED ROM MSB 8-Bit CRC Code MSB LSB 1-Wire Net DS1961S Available Commands: Read ROM Match ROM Search ROM Skip ROM Resume Overdrive Skip Overdrive Match Write Scratchpad ...
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... X MEMORY MAP The DS1961S has four memory areas: data memory, secrets memory, register page with special function registers and user-bytes, and a scratchpad. The data memory is organized in pages of 32 bytes. Secret, register page, and scratchpad are 8 bytes each. The scratchpad acts as a buffer when writing to the data memory, loading the initial secret or when writing to the register page ...
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... Register E read-only transfer-status register, used to verify data integrity with write commands. Since the scratchpad of the DS1961S is designed to accept data in blocks of eight bytes only, the lower three bits of TA1 are forced to 0 and the lower three bits of the E/S register (ending offset) always read 1. ...
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... DS1961S repeats the target address TA1 and TA2 and sends the contents of the E/S register. The partial flag (bit 5 of the E/S register) is set the last data byte the DS1961S received during a write scratchpad or refresh scratchpad command was incomplete there was a loss of power since data was last written to the scratchpad. The authorization-accepted (AA) flag (bit 7 of the E/S register) is normally cleared by a write scratchpad or refresh scratchpad ...
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... TA2), and all the data bytes. Note that the CRC16 calculation is performed with the actual TA1 sent by the master even though the DS1961S sets TA1 bits T2..T0 to 000b for the actual write scratchpad command. The master can end the write scratchpad command at any time. However, if the scratchpad is filled to its capacity, the master can send 16 read-time slots and receives the CRC generated by the DS1961S ...
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... The master should read through the end of the scratchpad after which it receives the inverted CRC that is computed with the data as sent by the DS1961S. If the master continues reading after the CRC all data is FFh. The scratchpad can be loaded using the write scratchpad or refresh scratchpad command. The data found in the scratchpad depends on the command used, the target address, and whether or not EPROM mode is active ...
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... Figure 7-1. MEMORY AND SHA FUNCTIONS FLOW CHART Bus Master TX Memory Function Command TA1 (T7:T0), TA2 (T15:T8) DS1961S Sets EN_LFS = 0 N Bus Master RX “1”s N Master TX Reset ? Y From ROM Functions Flow Chart (Figure 9) 0Fh N Write Scratch- pad ? Y Bus Master TX Y Address < ...
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... Byte Counter = 0 Bus Master RX Data Byte from Scratchpad Y Master TX Reset ? N N Byte Counter = Bus Master RX CRC16 of Command, Address, E/S Byte, Data Bytes as Sent by the DS1961S N Master TX Reset ? Figure 7 3rd Part Note: See the Read Scratchpad Description for Additional Information. From Figure 7 ...
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... First be Written to the Scratchpad Address of Secret ? N Address <7Fh ? EN_LFS Flag = 1 ? Duration 1-Wire Idle High for Power Figure 7 4th Part Y Y Write- Protected ? DS1961S Copies Scratch- PROG Pad Data to Address DS1961S TX “0” Y Master TX Reset ? N DS1961S TX “1” Master TX Reset ? Y From Figure 7 4th Part * N ...
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... Figure 7-4. MEMORY AND SHA FUNCTIONS FLOW CHART (continued) From Figure 7 3rd Part Compute Next Bus Master TX TA1 (T7:T0), TA2 (T15:T8) DS1961S Sets EN LFS = 0 N Bus Master RX “1”s Master TX Reset ? Y To Figure 7 3rd Part 33h N Secret ? Y Note: The Master Must First ...
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... Applicable to all R/W Memory Addresses SHA Engine Computes Message Authentication Code of Secret, 28 Bytes of Page Data, Scratchpad Data, and Device Identity Register Bus Master Computes MAC and Sends it to DS1961S Y N Bus Master Waits 10ms Y MAC Code Match ? DS1961S Copies Scratch- pad Data to Memory DS1961S TX “ ...
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... Y * 1-Wire Idle High for Power Figure 7 7th Part Note: Three Bytes of the Scratchpad Contents are Taken as a Challenge to the DS1961S. The Master can Specify the Challenge or Accept the Current Scratchpad Contents Instead. Duration: t SHA Engine Computes Message Authentication Code of Secret, Data of ...
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... Figure 7-7. MEMORY AND SHA FUNCTIONS FLOW CHART (continued) From Figure 7 6th Part Refresh Scratch- Bus Master TX TA1 (T7:T0), TA2 (T15:T8) DS1961S Sets EN_LFS = 0 N Bus Master RX “1”s N Master TX Reset ? Y The Flag is Set Only if Target Address is £ 7Fh. To Figure 7 6th Part ...
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... Figure 7-8. MEMORY AND SHA FUNCTIONS FLOW CHART (continued) From Figure 7 F0h 7th Part Read Memory ? Bus Master TX TA1 (T7:T0), TA2 (T15:T8) DS1961S Sets EN LFS = 0 Address < 98h ? To Figure 7 7th Part DS1961S Sets Memory Address = (T15:T0) Address Of Secret DS1961S Bus Master RX Increments ...
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... Some applications may require a higher level of security than can be achieved by a single, directly written secret. For additional security the DS1961S can compute a new secret based on the current secret, the contents of a selected memory page, and a partial secret that consists of all data in the scratchpad. To install a computed secret the master issues the compute next secret command, which activates the 512-bit SHA-1 engine, provided that the secret is not write-protected ...
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... DS1963S as a coprocessor. The coprocessor approach has the benefit that the secret remains hidden in the coprocessor iButton. The sequence in which the resulting MAC needs to be sent to the DS1961S is shown in Table 2. Tables 3A and 3B show how the various data components are entered into the SHA engine. The SHA computation algorithm is explained later in this document. ...
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... If the MAC generated by the DS1961S matches the MAC that the master computed, the DS1961S sets its AA flag, and copy the entire scratchpad contents to the data EEPROM. The master should read at least one byte at the conclusion of the copy delay. Reading AAh indicates that the copy was successful ...
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... The 160-bit MAC is transmitted in the same way as with the copy scratchpad command, Table 2, but the data flows from the DS1961S to the master. The data input to the SHA engine as it applies to the read authenticated page command is shown in Table 4. ...
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... After the master has issued the command code and specified the target addresses (TA1 and TA2), the DS1961S first clears the EN_LFS flag. If the target address is valid (< 0080h), the master receives the page data beginning at the target address through the end of the data page, one byte FFh and the inverted CRC of the command code, target address, transmitted page data and FFh byte. If the target address is invalid (³ ...
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... FFh bytes instead of the actual secret. After the master has issued the command code and specified the target addresses (TA1 and TA2), the DS1961S first clears the EN_LFS flag. If the target address is valid, the master reads data beginning from the target address and can continue until address 0097h ...
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SHA-1 COMPUTATION ALGORITHM This description of the SHA computation is adapted from the Secure Hash Standard SHA-1 document that can be downloaded from the NIST website (www.itl.nist.gov/fipspubs/fip180-1.htm). The algorithm takes as its input data sixteen 32-bit words ...
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... With the DS1961S the bus must be left low for no longer than 15.2µs at overdrive speed to ensure that none of the slave devices on the 1-Wire bus performs a reset. Despite of its limited compliance, the DS1961S communicates properly when used in conjunction with a DS2480B 1-Wire driver and serial port adapters that are based on this driver chip ...
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... All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1961S is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ...
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... Reset Pulse ? Y DS1961S TX Presence Pulse 55h N Match ROM Search ROM Command ? Command ? DS1961S TX Bit 0 DS1961S TX Bit 0 Master TX Bit Bit 0 Match ? Match ? Y DS1961S TX Bit 1 DS1961S TX Bit 1 Master TX Bit Bit 1 Match ? Match ? Y DS1961S TX Bit 63 DS1961S TX Bit 63 Master TX Bit Bit 63 Bit 63 Match ? Match ? Memory Functions ...
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Figure 9-2. ROM FUNCTIONS FLOW CHART To Figure 9, 1st Part From Figure 9 A5h 1st Part Resume Command ? From Figure 9 1st Part To Figure 9 1st Part 3Ch N N Overdrive ...
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... Resume Command [A5h typical application the DS1961S needs to be accessed several times to write a full 32-byte page multidrop environment this means that the 64-bit registration number of a match ROM command has to be repeated for every access. To maximize the data throughput in a multidrop environment the resume command function was implemented ...
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... ILMAX The initialization sequence required to begin any communication with the DS1961S is shown in Figure 10. A reset pulse followed by a presence pulse indicates the DS1961S is ready to receive data, given the correct ROM and memory function command mixed population network, the reset low time t needs to be long enough for the slowest 1-Wire slave device to recognize reset pulse ...
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... All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold V TL base creates a slave-sampling window that stretches from t at the sampling point determines whether the DS1961S decodes the time slot For reliable communication the voltage has to be either below the V the entire sampling window. Master-to-Slave ...
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... TL V ILMAX RESISTOR CRC GENERATION With the DS1961S there are two different types of CRCs. One CRC is an 8-bit type computed at the factory and lasered into the most significant byte of the 64-bit ROM. The equivalent polynomial function this CRC determine whether the ROM data has been read without error the bus ...
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... With write scratchpad, as well as refresh scratchpad, the CRC is generated by first clearing the CRC generator and then shifting in the command code, the target addresses TA1 (with set to 0) and TA2, and all data bytes as sent by the master. The DS1961S transmits this CRC only if the master has sent exactly eight bytes. ...
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ABSOLUTE MAXIMUM RATINGS* I/O Voltage to GND I/O Sink Current Temperature Range Junction Temperature Storage Temperature Range * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in ...
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PARAMETER SYMBOL Presence Detect High t PDH Time Presence Detect Low t PDL Time Presence Detect t MSP Sample Time I/O PIN, 1-WIRE WRITE Write-0 Low Time t W0L Write-1 Low Time t W1L Write Sample Time t SLS (Slave ...
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... MIN TYP MAX UNITS NOTES 4.5 mA 1.5 ms whenever the master drives the line low DS1961S VALUES STANDARD OVERDRIVE SPEED SPEED MIN MAX MIN 65µs (undef.) 9µs 720µs 960µs 68µs 15µs 60µs 1µs 60µ ...