DS1961S-F3 Maxim Integrated Products, DS1961S-F3 Datasheet - Page 21

• Manufacturer Part Number: DS1961S-F3
• Description: IBUTTON EEPROM 1KBit SHA-1 2CAN
• Manufacturer: Maxim Integrated Products
• Series: iButton®r

Specifications of DS1961S-F3

• Rohs Information: IButton RoHS Compliance Plan
• Memory Size: 128B
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

required. For practical use of the DS1961S as a monetary token, partial secrets are more critical than
being able to write-protect the secret or other areas of the device.
Table 3b. SHA-1 INPUT DATA FOR COPY SCRATCHPAD COMMAND WHEN
COPYING TO THE REGISTER PAGE OR SECRET
Legend
Read Authenticated Page [A5h]
The read authenticated page command provides the master with the data of a full or partial memory page
plus a MAC. The MAC allows the master to determine whether the secret stored in the DS1961S is valid
within the application. The DS1961S computes the MAC from its secret, all the data of the selected
memory page, the first seven bytes of the identity register and a 3-byte challenge, which the master
should write to the scratchpad prior to issuing the read authenticated page command. To do this, the
master can use the write scratchpad command with any target address within the data memory. The
relevant portions of the challenge are the 5th, 6
data that happens to reside in the scratchpad from a previous command as a challenge. The 160-bit MAC
is transmitted in the same way as with the copy scratchpad command, Table 2, but the data flows from the
DS1961S to the master. The data input to the SHA engine as it applies to the read authenticated page
command is shown in Table 4.
M0[31:24] = (SS + 0)
M1[31:24] = (SS + 0)
M2[31:24] = (SS + 4)
M3[31:24] = (RP + 0)
M4[31:24] = (RP + 4)
M5[31:24] = (ID + 0)
M6[31:24] = (ID + 4)
M7[31:24] = FFh
M8[31:24] = (SP + 0)
M9[31:24] = (SP + 4)
M10[31:24] = MP
M11[31:24] = (ID + 3) M11[23:16] = (ID + 4) M11[15:8] = (ID + 5)
M12[31:24] = (SS + 4) M12[23:16] = (SS + 5) M12[15:8] = (SS + 6)
M13[31:24] = FFh
M14[31:24] = 00h
M15[31:24] = 00h
Mt
(SS + N)
(RP + N) Byte N of Register Page; Page Begins at 0088h
(SP + N)
MP
(ID + N)
M5[23:16] = (ID + 1)
M6[23:16] = (ID + 5)
M10[23:16] = (ID + 0) M10[15:8] = (ID + 1)
M0[23:16] = (SS + 1)
M1[23:16] = (SS + 1)
M2[23:16] = (SS + 5)
M3[23:16] = (RP + 1)
M4[23:16] = (RP + 5)
M7[23:16] = FFh
M8[23:16] = (SP + 1)
M9[23:16] = (SP + 5)
M13[23:16] = FFh
M14[23:16] = 00h
M15[23:16] = 00h
Input Buffer of SHA Engine
0 £ t £ 15; 32-Bit Words
Byte N of Secret; Secret Begins at Address 0080h
(see Memory Map)
(see Memory Map)
Byte N of Scratchpad
MP[7:0] = 04h
Byte N of Identity Register
th
, and 7th bytes. Alternatively, the master can accept the
21 of 36
M5[15:8] = (ID + 2)
M6[15:8] = (ID + 6)
M0[15:8] = (SS + 2)
M1[15:8] = (SS + 2)
M2[15:8] = (SS + 6)
M3[15:8] = (RP + 2)
M4[15:8] = (RP + 6)
M7[15:8] = FFh
M8[15:8] = (SP + 2)
M9[15:8] = (SP + 6)
M13[15:8] = FFh
M14[15:8] = 00h
M15[15:8] = 01h
M5[7:0] = (ID + 3)
M6[7:0] = (ID + 7)
M10[7:0] = (ID + 2)
M12[7:0] = (SS + 7)
M0[7:0] = (SS + 3)
M1[7:0] = (SS + 3)
M2[7:0] = (SS + 7)
M3[7:0] = (RP + 3)
M4[7:0] = (RP + 7)
M7[7:0] = FFh
M8[7:0] = (SP + 3)
M9[7:0] = (SP + 7)
M11[7:0] = (ID + 6)
M13[7:0] = 80h
M14[7:0] = 00h
M15[7:0] = B8h