DS1961S-F3 Maxim Integrated Products, DS1961S-F3 Datasheet - Page 33

• Manufacturer Part Number: DS1961S-F3
• Description: IBUTTON EEPROM 1KBit SHA-1 2CAN
• Manufacturer: Maxim Integrated Products
• Series: iButton®r

Specifications of DS1961S-F3

• Rohs Information: IButton RoHS Compliance Plan
• Memory Size: 128B
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

read from the DS1961S. This 8-bit CRC is received in the true form (noninverted) when reading the
ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function
X
when reading the scratchpad and for fast verification of a data transfer when writing to the scratchpad or
with refresh scratchpad. It is the same type of CRC as is used for error detection within the iButton
extended file structure. In contrast to the 8-bit CRC, the 16-bit CRC is always returned or sent in the
complemented (inverted) form. A CRC-generator inside the DS1961S chip (Figure 12) calculates a new
16-bit CRC as shown in the command flow chart of Figure 7. The bus master can compare the CRC value
read from the device to the one it calculates from the data and decide whether to continue with an
operation or to re-read the portion of the data with the CRC error.
With write scratchpad, as well as refresh scratchpad, the CRC is generated by first clearing the CRC
generator and then shifting in the command code, the target addresses TA1 (with T2 to T0 set to 0) and
TA2, and all data bytes as sent by the master. The DS1961S transmits this CRC only if the master has
sent exactly eight bytes.
With the read scratchpad command the CRC is generated by first clearing the CRC generator and then
shifting in the command code, the target addresses TA1 and TA2, the E/S byte, and the scratchpad data,
which may have been modified by the DS1961S (see write scratchpad command). The DS1961S
transmits this CRC only if the reading continues through the end of the scratchpad.
With the read authenticated page command the 16-bit CRC value is the result of shifting the command
byte into the cleared CRC generator, followed by the two address bytes, the data bytes, and the FFh byte.
The CRC that follows the MAC results from clearing the CRC generator and then shifting in the 160-bit
MAC in the same bit sequence as the master receives it.
For more details on generating CRC values including example implementations in both hardware and
software, refer to The Book of DS19xx iButton Standards.
Figure 12. CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL
16
X
X
0
8
+ X
STAGE
STAGE
9
1
th
st
15
+ X
X
X
9
1
STAGE
STAGE
2
10
2
+ 1. This CRC is used for error detection with the read authenticated page command,
nd
th
X
10
STAGE
11
th
X
11
STAGE
X
12
2
STAGE
th
3
Polynomial = X
rd
X
12
STAGE
X
13
3
STAGE
th
4
th
X
13
33 of 36
STAGE
X
14
16
4
STAGE
+ X
th
5
th
X
15
14
+ X
STAGE
X
15
5
STAGE
2
th
+ 1
6
th
INPUT DATA
X
6
STAGE
7
th
X
X
15
7
STAGE
STAGE
16
8
th
th
X
16
CRC
OUTPUT