DS1961S-F3 Maxim Integrated Products, DS1961S-F3 Datasheet - Page 7

• Manufacturer Part Number: DS1961S-F3
• Description: IBUTTON EEPROM 1KBit SHA-1 2CAN
• Manufacturer: Maxim Integrated Products
• Series: iButton®r

Specifications of DS1961S-F3

• Rohs Information: IButton RoHS Compliance Plan
• Memory Size: 128B
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS1961S
This indicates that all the data in the scratchpad is used for a subsequent copying into main memory or
secret. Bit 5 of the E/S register, called PF or partial byte flag, is a logic-1 if the number of data bits sent
by the master is not an integer multiple of eight or if the data in the scratchpad is not valid due to a loss of
power. A valid write to the scratchpad clears the PF bit. Bits 3, 4, and 6 have no function; they always
read 1. The partial flag supports the master checking the data integrity after a write command. The
highest valued bit of the E/S register is called the AA or authorization accepted flag, which indicates that
the data stored in the scratchpad has already been copied to the target memory address. Writing data to
the scratchpad clears this flag.
WRITING WITH VERIFICATION
To write data to the DS1961S, the scratchpad has to be used as intermediate storage. First the master
issues the write scratchpad command, which specifies the desired target address and the data to be written
to the scratchpad. Note that writes to data memory must be performed on 8-byte boundaries with the three
LSBs of the target address T2–T0 equal to 000b. Therefore, if T2–T0 are sent with non-zero values, the
device sets these bits to zero and uses the modified address as the target address. The master should
always send eight complete data bytes. After the eight bytes of data have been transmitted, the master can
elect to receive an inverted CRC16 of the write scratchpad command, the address as sent by the master,
and the data as sent by the master. The master can compare the CRC to the value it has calculated itself in
order to determine if the communication was successful. After the scratchpad has been written, the master
should always perform a read scratchpad to verify that the intended data was in fact written. During a
read scratchpad, the DS1961S repeats the target address TA1 and TA2 and sends the contents of the E/S
register. The partial flag (bit 5 of the E/S register) is set to 1 if the last data byte the DS1961S received
during a write scratchpad or refresh scratchpad command was incomplete, or if there was a loss of power
since data was last written to the scratchpad. The authorization-accepted (AA) flag (bit 7 of the E/S
register) is normally cleared by a write scratchpad or refresh scratchpad; therefore, if it is set to 1, it
indicates that the DS1961S did not understand the proceeding write (or refresh) scratchpad command. In
either of these cases, the master should rewrite the scratchpad. After the master receives the E/S register,
the scratchpad data is received. The descriptions of write scratchpad and refresh scratchpad provide
clarification of what changes can occur to the scratchpad data under certain conditions. An inverted CRC
of the read scratchpad command, target address, E/S register, and scratchpad data follows the scratchpad
data. As with the write scratchpad command, this CRC can be compared to the value the master has
calculated itself in order to determine if the communication was successful. After the master has verified
the data, it can send the copy scratchpad to copy the scratchpad to memory. Alternatively, the load first
secret or compute next secret command can be issued to change the secret. See the descriptions of these
commands for more information.
In a touch environment the quality of the electrical contact cannot be guaranteed. With poor or
intermittent contact it is possible for a copy scratchpad command to complete with insufficient energy,
leaving the floating gate voltage of an EEPROM bit in the area of the threshold between 0 and 1. When
this occurs, the logical value of the bit is not assured. Depending on voltage and/or temperature
conditions, the same bit can be read by the host as one polarity and then by the internal SHA-1 engine as
the opposite polarity. This becomes a fatal lockup mode because the host cannot formulate a proper SHA-
1 MAC to enable the bit to be rewritten. To repair poorly written bits and thereby restore the device to
functionality, the refresh scratchpad command was introduced. Combined with the load first secret
command, refresh scratchpad provides a means to restore the EEPROM bits to normal values, removing
lockup conditions and allowing the device to be written again.
To prevent the occurrence of poorly written bits, a refresh sequence should be performed after each copy
scratchpad command. A refresh sequence is defined as a refresh scratchpad (to the same target address as
the previous copy scratchpad), followed by a load first secret. The EN_LFS flag is set by the refresh
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