MT16LSDT6464AG-133D2 Micron Technology Inc, MT16LSDT6464AG-133D2 Datasheet - Page 21
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MT16LSDT6464AG-133D2
Manufacturer Part Number
MT16LSDT6464AG-133D2
Description
MODULE SDRAM 512MB 168DIMM
Manufacturer
Micron Technology Inc
Specifications of MT16LSDT6464AG-133D2
Memory Type
SDRAM
Memory Size
512MB
Speed
133MHz
Package / Case
168-DIMM
Main Category
DRAM Module
Sub-category
SDRAM
Module Type
168UDIMM
Device Core Size
64b
Organization
64Mx64
Total Density
512MByte
Chip Density
256Mb
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Operating Current
1.096A
Number Of Elements
16
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
168
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 20: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Table 21: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
NOTE:
09005aef80bccbe7
SD8_16C16_32x64AG.fm - Rev. E 12/05 EN
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
PARAMETER/CONDITION
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: I
INPUT LEAKAGE CURRENT: V
OUTPUT LEAKAGE CURRENT: V
STANDBY CURRENT: SCL = SDA = V
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
edge of SDA.
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
OUT
SS
SS
IN
; V
; V
= 3mA
OUT
= GND to V
DDSPD
DDSPD
DD
= GND to V
= +2.3V to +3.6V
- 0.3V; All other inputs = V
= +2.3V to +3.6V
t
WRC) is the time from a valid stop condition of a write sequence to the end of
DD
DD
21
128MB (x64, SR), 256MB (x64, DR)
DD
or V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SYMBOL
SS
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
t
HIGH
LOW
f
WRC
t
t
BUF
SCL
AA
DH
t
t
t
SYMBOL
F
R
I
V
DDSPD
Vih
V
I
V
I
I
I
168-PIN SDRAM UDIMM
LO
CC
SB
OL
LI
IL
V
MIN
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
DDSPD
0
MIN
©2003, 2004 Micron Technology, Inc. All rights reserved.
2.3
-1
–
–
–
–
–
MAX
× 0.7 V
300
400
0.9
0.3
50
10
V
UNITS
DDSPD
DDSPD
KHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
MAX
3.6
0.4
10
10
30
2
+ 0.5
× 0.3
NOTES
UNITS
1
2
2
3
4
mA
µA
µA
µA
V
V
V
V